From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, bcain@quicinc.com, philmd@redhat.com,
richard.henderson@linaro.org, laurent@vivier.eu,
tsimpson@quicinc.com, alex.bennee@linaro.org
Subject: [PATCH v7 28/35] Hexagon (target/hexagon) TCG for floating point instructions
Date: Tue, 19 Jan 2021 21:29:01 -0600 [thread overview]
Message-ID: <1611113349-24906-29-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1611113349-24906-1-git-send-email-tsimpson@quicinc.com>
The imported code uses host floating point. We override them
to use qemu softfloat
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 121 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index a8d9321..e044dea 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -195,4 +195,125 @@
#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
+/* Floating point */
+#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
+ gen_helper_conv_sf2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
+ gen_helper_conv_df2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
+ gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
+ gen_helper_conv_uw2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
+ gen_helper_conv_w2sf(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
+ gen_helper_conv_w2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
+ gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
+ gen_helper_conv_ud2df(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
+ gen_helper_conv_d2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
+ gen_helper_conv_d2df(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
+ gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
+ gen_helper_conv_sf2w(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
+ gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
+ gen_helper_conv_sf2d(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
+ gen_helper_conv_df2uw(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
+ gen_helper_conv_df2w(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
+ gen_helper_conv_df2ud(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
+ gen_helper_conv_df2d(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
+ gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
+ gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
+ gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
+ gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
+ gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
+ gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
+ gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
+ gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_sfadd(SHORTCODE) \
+ gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfsub(SHORTCODE) \
+ gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
+ gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
+ gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
+ gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
+ gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfmax(SHORTCODE) \
+ gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfmin(SHORTCODE) \
+ gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfclass(SHORTCODE) \
+ do { \
+ TCGv imm = tcg_const_tl(uiV); \
+ gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
+ tcg_temp_free(imm); \
+ } while (0)
+#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
+ gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
+ gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
+ gen_helper_sffixupr(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_dfadd(SHORTCODE) \
+ gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfsub(SHORTCODE) \
+ gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmax(SHORTCODE) \
+ gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmin(SHORTCODE) \
+ gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
+ gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
+ gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
+ gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
+ gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfclass(SHORTCODE) \
+ do { \
+ TCGv imm = tcg_const_tl(uiV); \
+ gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
+ tcg_temp_free(imm); \
+ } while (0)
+#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
+ gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffma(SHORTCODE) \
+ gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
+ gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
+#define fGEN_TCG_F2_sffms(SHORTCODE) \
+ gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
+ gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
+ gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
+
+#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
+ gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
+ gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+
#endif
--
2.7.4
next prev parent reply other threads:[~2021-01-20 3:53 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-20 3:28 [PATCH v7 00/35] Hexagon patch series Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 01/35] Hexagon Update MAINTAINERS file Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 02/35] Hexagon (target/hexagon) README Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 03/35] Hexagon (include/elf.h) ELF machine definition Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 04/35] Hexagon (target/hexagon) scalar core definition Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 05/35] Hexagon (disas) disassembler Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 06/35] Hexagon (target/hexagon) register names Taylor Simpson
2021-01-22 17:46 ` Philippe Mathieu-Daudé
2021-01-20 3:28 ` [PATCH v7 07/35] Hexagon (target/hexagon) scalar core helpers Taylor Simpson
2021-01-22 20:30 ` Philippe Mathieu-Daudé
2021-01-22 21:44 ` Philippe Mathieu-Daudé
2021-01-22 21:50 ` Taylor Simpson
2021-01-25 16:16 ` Philippe Mathieu-Daudé
2021-01-20 3:28 ` [PATCH v7 08/35] Hexagon (target/hexagon) GDB Stub Taylor Simpson
2021-01-22 17:48 ` Philippe Mathieu-Daudé
2021-01-20 3:28 ` [PATCH v7 09/35] Hexagon (target/hexagon) architecture types Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 10/35] Hexagon (target/hexagon) instruction and packet types Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 11/35] Hexagon (target/hexagon) register fields Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 12/35] Hexagon (target/hexagon) instruction attributes Taylor Simpson
2021-01-22 17:53 ` Philippe Mathieu-Daudé
2021-01-22 22:01 ` Taylor Simpson
2021-01-25 16:21 ` Philippe Mathieu-Daudé
2021-01-29 23:15 ` Taylor Simpson
2021-02-05 17:35 ` Philippe Mathieu-Daudé
2021-01-20 3:28 ` [PATCH v7 13/35] Hexagon (target/hexagon) instruction/packet decode Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 14/35] Hexagon (target/hexagon) instruction printing Taylor Simpson
2021-01-22 17:58 ` Philippe Mathieu-Daudé
2021-01-22 18:10 ` Eric Blake
2021-01-20 3:28 ` [PATCH v7 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions Taylor Simpson
2021-01-22 18:09 ` Philippe Mathieu-Daudé
2021-01-22 21:59 ` Taylor Simpson
2021-01-25 16:29 ` Philippe Mathieu-Daudé
2021-01-25 21:43 ` Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 16/35] Hexagon (target/hexagon/conv_emu.[ch]) " Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 17/35] Hexagon (target/hexagon/fma_emu.[ch]) " Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 18/35] Hexagon (target/hexagon/imported) arch import Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 19/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 20/35] Hexagon (target/hexagon) generator phase 2 - generate header files Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 21/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 22/35] Hexagon (target/hexagon) generater phase 4 - " Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 23/35] Hexagon (target/hexagon) opcode data structures Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 24/35] Hexagon (target/hexagon) macros Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 25/35] Hexagon (target/hexagon) instruction classes Taylor Simpson
2021-01-20 3:28 ` [PATCH v7 26/35] Hexagon (target/hexagon) TCG generation Taylor Simpson
2021-01-20 3:29 ` [PATCH v7 27/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions Taylor Simpson
2021-01-20 3:29 ` Taylor Simpson [this message]
2021-01-20 3:29 ` [PATCH v7 29/35] Hexagon (target/hexagon) translation Taylor Simpson
2021-01-20 3:29 ` [PATCH v7 30/35] Hexagon (linux-user/hexagon) Linux user emulation Taylor Simpson
2021-02-17 20:15 ` Laurent Vivier
2021-02-17 21:10 ` Richard Henderson
2021-01-20 3:29 ` [PATCH v7 31/35] Hexagon (tests/tcg/hexagon) TCG tests - multiarch Taylor Simpson
2021-01-20 3:29 ` [PATCH v7 32/35] Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Taylor Simpson
2021-01-20 3:29 ` [PATCH v7 33/35] Hexagon (tests/tcg/hexagon) TCG tests - floating point Taylor Simpson
2021-01-20 3:29 ` [PATCH v7 34/35] Hexagon build infrastructure Taylor Simpson
2021-01-22 22:34 ` Philippe Mathieu-Daudé
2021-01-22 22:41 ` Philippe Mathieu-Daudé
2021-01-22 22:44 ` Philippe Mathieu-Daudé
2021-01-27 19:16 ` Taylor Simpson
2021-01-20 3:29 ` [PATCH v7 35/35] Add Dockerfile for hexagon Taylor Simpson
2021-01-20 4:13 ` [PATCH v7 00/35] Hexagon patch series no-reply
2021-01-25 22:14 ` Philippe Mathieu-Daudé
2021-01-25 23:09 ` Taylor Simpson
2021-01-25 23:28 ` Brian Cain
2021-03-17 0:08 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1611113349-24906-29-git-send-email-tsimpson@quicinc.com \
--to=tsimpson@quicinc.com \
--cc=ale@rev.ng \
--cc=alex.bennee@linaro.org \
--cc=bcain@quicinc.com \
--cc=laurent@vivier.eu \
--cc=philmd@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).