From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Bin Meng <bin.meng@windriver.com>,
Francisco Iglesias <francisco.iglesias@xilinx.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Xuzhou Cheng <xuzhou.cheng@windriver.com>
Subject: [PATCH v3 5/5] hw/ssi: xilinx_spips: Remove DMA related code from zynqmp_qspips
Date: Wed, 10 Feb 2021 18:10:13 +0800 [thread overview]
Message-ID: <1612951813-50542-6-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com>
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Now that the XLNX CSU DMA model is implemented, the existing codes
in the ZynqMP QSPIS are useless and should be removed.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v3:
- new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips
hw/ssi/xilinx_spips.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 8a0cc22..1e9dba2 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -195,13 +195,6 @@
#define R_GQSPI_MOD_ID (0x1fc / 4)
#define R_GQSPI_MOD_ID_RESET (0x10a0000)
-#define R_QSPIDMA_DST_CTRL (0x80c / 4)
-#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00)
-#define R_QSPIDMA_DST_I_MASK (0x820 / 4)
-#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
-#define R_QSPIDMA_DST_CTRL2 (0x824 / 4)
-#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8)
-
/* size of TXRX FIFOs */
#define RXFF_A (128)
#define TXFF_A (128)
@@ -417,9 +410,6 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
s->regs[R_GQSPI_GPIO] = 1;
s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
- s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET;
- s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET;
- s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET;
s->man_start_com_g = false;
s->gqspi_irqline = 0;
xlnx_zynqmp_qspips_update_ixr(s);
--
2.7.4
next prev parent reply other threads:[~2021-02-10 10:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-10 10:10 [PATCH v3 0/5] hw/arm: zynqmp: Implement a CSU DMA model and connect it with GQSPI Bin Meng
2021-02-10 10:10 ` [PATCH v3 1/5] hw/dma: xlnx_csu_dma: Implement a basic XLNX CSU DMA model Bin Meng
2021-02-10 11:52 ` Edgar E. Iglesias
2021-02-10 10:10 ` [PATCH v3 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Bin Meng
2021-02-10 11:54 ` Edgar E. Iglesias
2021-02-10 10:10 ` [PATCH v3 3/5] hw/arm: xlnx-zynqmp: Add XLNX CSU DMA module Bin Meng
2021-02-10 11:38 ` Edgar E. Iglesias
2021-02-10 10:10 ` [PATCH v3 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Bin Meng
2021-02-10 11:39 ` Edgar E. Iglesias
2021-02-10 10:10 ` Bin Meng [this message]
2021-02-10 11:39 ` [PATCH v3 5/5] hw/ssi: xilinx_spips: Remove DMA related code from zynqmp_qspips Edgar E. Iglesias
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