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From: Nicholas Piggin <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>, qemu-ppc@nongnu.org
Cc: "Fabiano Rosas" <farosas@linux.ibm.com>,
	"Cédric Le Goater" <clg@fr.ibm.com>,
	qemu-devel@nongnu.org,
	"David Gibson" <david@gibson.dropbear.id.au>
Subject: Re: [EXTERNAL] [RFC PATCH 2/2] target/ppc: Add POWER10 exception model
Date: Thu, 15 Apr 2021 15:28:20 +1000	[thread overview]
Message-ID: <1618464352.9ndmtpt9ct.astroid@bobo.none> (raw)
In-Reply-To: <07285365-1c95-27b3-6922-260709d22624@kaod.org>

Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am:
> On 4/14/21 5:23 AM, Nicholas Piggin wrote:
>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
>> and it removes support for the LPCR[AIL]=0b10 mode.
> 
> This looks good but it's missing the MSR_LE setting. A part from that : 

Oh, and lpes as well. Looks like a mis-merged from my original patch.
Thanks for catching it, great.

> 
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> 
> and 
> 
> Tested-by: Cédric Le Goater <clg@kaod.org>

Thanks, this was tested after you added the MSR_LE bit?
> 
> distros using scv on P10 now need your patch to boot :
> 
> "powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors"
> 
> I guess it will get merged in time. 

Yes, unfortunately. Real hardware crashes the same way though, so
nothing to be done about it.

Thanks,
Nick


  reply	other threads:[~2021-04-15  5:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14  3:23 [RFC PATCH 0/2] ppc: rework AIL logic, add POWER10 exception model Nicholas Piggin
2021-04-14  3:23 ` [RFC PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery Nicholas Piggin
2021-04-14 15:24   ` [EXTERNAL] " Cédric Le Goater
2021-04-15  5:25     ` Nicholas Piggin
2021-04-14  3:23 ` [RFC PATCH 2/2] target/ppc: Add POWER10 exception model Nicholas Piggin
2021-04-14 15:54   ` [EXTERNAL] " Cédric Le Goater
2021-04-15  5:28     ` Nicholas Piggin [this message]
2021-04-15  6:50       ` Cédric Le Goater

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