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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Fri, 26 Jan 2018 11:03:43 -0800
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Subject: Re: [Qemu-devel] [PATCH v2 09/11] target/arm: Decode aa64 armv8.3
 fcmla
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, qemu-arm <qemu-arm@nongnu.org>

On 01/26/2018 02:07 AM, Peter Maydell wrote:
>> The SVE pseudocode for the same operation is clearer than that in the main ARM
>> ARM, and is nearer to what I used:
>>
>>   for e = 0 to elements-1
>>     if ElemP[mask, e, esize] == '1' then
>>         pair = e - (e MOD 2);  // index of first element in pair
>>         addend = Elem[result, e, esize];
>>         if IsEven(e) then  // real part
>>             // realD = realA [+-] flip ? (imagN * imagM) : (realN * realM)
>>             element1 = Elem[operand1, pair + flip, esize];
>>             element2 = Elem[operand2, pair + flip, esize];
>>             if neg_real then element2 = FPNeg(element2);
>>         else  // imaginary part
>>             // imagD = imagA [+-] flip ? (imagN * realM) : (realN * imagM)
>>             element1 = Elem[operand1, pair + flip, esize];
>>             element2 = Elem[operand2, pair + (1 - flip), esize];
>>             if neg_imag then element2 = FPNeg(element2);
>>         Elem[result, e, esize] = FPMulAdd(addend, element1, element2, FPCR);
>>
>> In my version, e0/e1 are element1/element2 (real) and e2/e3 are
>> element1/element2 (imag).
> 
> Thanks. Could we use the same indexing (1/2/3/4) as the final Arm ARM
> pseudocode?

Done.


r~