* [PATCH 1/2] Hexagon (target/hexagon) fix bug in fLSBNEW*
[not found] <1621378722-4474-1-git-send-email-tsimpson@quicinc.com>
@ 2021-05-18 22:58 ` Taylor Simpson
2021-05-18 22:58 ` [PATCH 2/2] Hexagon (target/hexagon) fix l2fetch instructions Taylor Simpson
1 sibling, 0 replies; 3+ messages in thread
From: Taylor Simpson @ 2021-05-18 22:58 UTC (permalink / raw)
To: tsimpson; +Cc: open list:All patches CC here
Change fLSBNEW/fLSBNEW0/fLSBNEW1 from copy to "x & 1"
Remove gen_logical_not function
Clean up fLSBNEWNOT to use andi-1 followed by xori-1
Test cases added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/macros.h | 27 ++++++++++-----------------
target/hexagon/op_helper.c | 5 -----
tests/tcg/hexagon/misc.c | 39 ++++++++++++++++++++++++++++++++++++++-
3 files changed, 48 insertions(+), 23 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index b726c3b..2b208f3 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -239,33 +239,26 @@ static inline void gen_pred_cancel(TCGv pred, int slot_num)
#endif
#ifdef QEMU_GENERATE
-#define fLSBNEW(PVAL) tcg_gen_mov_tl(LSB, (PVAL))
-#define fLSBNEW0 tcg_gen_mov_tl(LSB, hex_new_pred_value[0])
-#define fLSBNEW1 tcg_gen_mov_tl(LSB, hex_new_pred_value[1])
+#define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1)
+#define fLSBNEW0 tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
+#define fLSBNEW1 tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
#else
-#define fLSBNEW(PVAL) (PVAL)
-#define fLSBNEW0 new_pred_value(env, 0)
-#define fLSBNEW1 new_pred_value(env, 1)
+#define fLSBNEW(PVAL) ((PVAL) & 1)
+#define fLSBNEW0 (env->new_pred_value[0] & 1)
+#define fLSBNEW1 (env->new_pred_value[1] & 1)
#endif
#ifdef QEMU_GENERATE
-static inline void gen_logical_not(TCGv dest, TCGv src)
-{
- TCGv one = tcg_const_tl(1);
- TCGv zero = tcg_const_tl(0);
-
- tcg_gen_movcond_tl(TCG_COND_NE, dest, src, zero, zero, one);
-
- tcg_temp_free(one);
- tcg_temp_free(zero);
-}
#define fLSBOLDNOT(VAL) \
do { \
tcg_gen_andi_tl(LSB, (VAL), 1); \
tcg_gen_xori_tl(LSB, LSB, 1); \
} while (0)
#define fLSBNEWNOT(PNUM) \
- gen_logical_not(LSB, (PNUM))
+ do { \
+ tcg_gen_andi_tl(LSB, (PNUM), 1); \
+ tcg_gen_xori_tl(LSB, LSB, 1); \
+ } while (0)
#else
#define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
#define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 63dd685..4595559 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -128,11 +128,6 @@ void HELPER(debug_start_packet)(CPUHexagonState *env)
}
}
-static int32_t new_pred_value(CPUHexagonState *env, int pnum)
-{
- return env->new_pred_value[pnum];
-}
-
/* Checks for bookkeeping errors between disassembly context and runtime */
void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
{
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index 17c3919..9e139f3 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -181,6 +181,19 @@ static inline void S4_storeirifnew_io(void *p, int pred)
: "p0", "memory");
}
+static int L2_ploadrifnew_pi(void *p, int pred)
+{
+ int result;
+ asm volatile("%0 = #31\n\t"
+ "{\n\t"
+ " p0 = cmp.eq(%1, #1)\n\t"
+ " if (!p0.new) %0 = memw(%2++#4)\n\t"
+ "}\n\t"
+ : "=r"(result) : "r"(pred), "r"(p)
+ : "p0");
+ return result;
+}
+
/*
* Test that compound-compare-jump is executed in 2 parts
* First we have to do all the compares in the packet and
@@ -298,8 +311,24 @@ static int auto_and(void)
return retval;
}
+void test_lsbnew(void)
+{
+ int result;
+
+ asm("r0 = #2\n\t"
+ "r1 = #5\n\t"
+ "{\n\t"
+ " p0 = r0\n\t"
+ " if (p0.new) r1 = #3\n\t"
+ "}\n\t"
+ "%0 = r1\n\t"
+ : "=r"(result) :: "r0", "r1", "p0");
+ check(result, 5);
+}
+
int main()
{
+ int res;
long long res64;
int pred;
@@ -394,6 +423,12 @@ int main()
S4_storeirifnew_io(&array[8], 1);
check(array[9], 9);
+ memcpy(array, init, sizeof(array));
+ res = L2_ploadrifnew_pi(&array[6], 0);
+ check(res, 6);
+ res = L2_ploadrifnew_pi(&array[7], 1);
+ check(res, 31);
+
int x = cmpnd_cmp_jump();
check(x, 12);
@@ -406,7 +441,7 @@ int main()
check((int)pair, 5);
check((int)(pair >> 32), 7);
- int res = test_clrtnew(1, 7);
+ res = test_clrtnew(1, 7);
check(res, 0);
res = test_clrtnew(2, 7);
check(res, 7);
@@ -422,6 +457,8 @@ int main()
res = auto_and();
check(res, 0);
+ test_lsbnew();
+
puts(err ? "FAIL" : "PASS");
return err;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 2/2] Hexagon (target/hexagon) fix l2fetch instructions
[not found] <1621378722-4474-1-git-send-email-tsimpson@quicinc.com>
2021-05-18 22:58 ` [PATCH 1/2] Hexagon (target/hexagon) fix bug in fLSBNEW* Taylor Simpson
@ 2021-05-18 22:58 ` Taylor Simpson
1 sibling, 0 replies; 3+ messages in thread
From: Taylor Simpson @ 2021-05-18 22:58 UTC (permalink / raw)
To: tsimpson; +Cc: open list:All patches CC here
Y4_l2fetch == l2fetch(Rs32, Rt32)
Y5_l2fetch == l2fetch(Rs32, Rtt32)
The semantics for these instructions are present, but the encodings
are missing.
Note that these are treated as nops in qemu, so we add overrides.
Test case added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 11 +++++++++++
tests/tcg/hexagon/misc.c | 9 +++++++++
target/hexagon/imported/encode_pp.def | 3 +++
3 files changed, 23 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 18fcdbc..a375d6a 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -734,4 +734,15 @@
#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+/* Nothing to do for these in qemu, need to suppress compiler warnings */
+#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ RtV = RtV; \
+ } while (0)
+#define fGEN_TCG_Y5_l2fetch(SHORTCODE) \
+ do { \
+ RsV = RsV; \
+ } while (0)
+
#endif
diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c
index 9e139f3..f0b1947 100644
--- a/tests/tcg/hexagon/misc.c
+++ b/tests/tcg/hexagon/misc.c
@@ -326,6 +326,13 @@ void test_lsbnew(void)
check(result, 5);
}
+void test_l2fetch(void)
+{
+ /* These don't do anything in qemu, just make sure they don't assert */
+ asm volatile ("l2fetch(r0, r1)\n\t"
+ "l2fetch(r0, r3:2)\n\t");
+}
+
int main()
{
int res;
@@ -459,6 +466,8 @@ int main()
test_lsbnew();
+ test_l2fetch();
+
puts(err ? "FAIL" : "PASS");
return err;
}
diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def
index 35ae3d2..939c6fc 100644
--- a/target/hexagon/imported/encode_pp.def
+++ b/target/hexagon/imported/encode_pp.def
@@ -493,6 +493,9 @@ DEF_ENC32(Y2_dccleana, ICLASS_ST" 000 00 00sssss PP------ --------")
DEF_ENC32(Y2_dcinva, ICLASS_ST" 000 00 01sssss PP------ --------")
DEF_ENC32(Y2_dccleaninva, ICLASS_ST" 000 00 10sssss PP------ --------")
+DEF_ENC32(Y4_l2fetch, ICLASS_ST" 011 00 00sssss PP-ttttt 000-----")
+DEF_ENC32(Y5_l2fetch, ICLASS_ST" 011 01 00sssss PP-ttttt --------")
+
/*******************************/
/* */
/* */
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread