From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@gmail.com,
richard.henderson@linaro.org, f4bug@amsat.org,
maobibo@loongson.cn, laurent@vivier.eu, yangxiaojuan@loongson.cn,
alistair.francis@wdc.com, pbonzini@redhat.com,
alex.bennee@linaro.org
Subject: [PATCH v3 09/19] target/loongarch: Add fixed point extra instruction translation
Date: Fri, 27 Aug 2021 15:14:44 +0800 [thread overview]
Message-ID: <1630048494-2143-10-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1630048494-2143-1-git-send-email-gaosong@loongson.cn>
This patch implement fixed point extra instruction translation.
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/helper.h | 4 ++
| 88 +++++++++++++++++++++++++++++++
target/loongarch/insns.decode | 25 +++++++++
target/loongarch/op_helper.c | 26 +++++++++
target/loongarch/translate.c | 1 +
5 files changed, 144 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_extra.c
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 09b5a3d..e4b4595 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -14,3 +14,7 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_3(asrtle_d, void, env, tl, tl)
DEF_HELPER_3(asrtgt_d, void, env, tl, tl)
+
+DEF_HELPER_3(crc32, tl, tl, tl, tl)
+DEF_HELPER_3(crc32c, tl, tl, tl, tl)
+DEF_HELPER_2(cpucfg, tl, env, tl)
--git a/target/loongarch/insn_trans/trans_extra.c b/target/loongarch/insn_trans/trans_extra.c
new file mode 100644
index 0000000..d07e791
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_extra.c
@@ -0,0 +1,88 @@
+/*
+ * LoongArch translate functions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+static bool trans_break(DisasContext *ctx, arg_break *a)
+{
+ generate_exception(ctx, EXCP_BREAK);
+ return true;
+}
+
+static bool trans_syscall(DisasContext *ctx, arg_syscall *a)
+{
+ generate_exception(ctx, EXCP_SYSCALL);
+ return true;
+}
+
+static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ return true;
+}
+
+static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ return true;
+}
+
+static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
+{
+ tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
+ return true;
+}
+
+static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
+{
+ tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
+ return true;
+}
+
+static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
+{
+ tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
+ return true;
+}
+
+static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ gen_helper_cpucfg(dest, cpu_env, src1);
+ return true;
+}
+
+static bool gen_crc(DisasContext *ctx, arg_fmt_rdrjrk *a,
+ void (*func)(TCGv, TCGv, TCGv, TCGv),
+ TCGv tsz)
+{
+ ctx->dst_ext = EXT_SIGN;
+ TCGv dest = gpr_dst(ctx, a->rd);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+
+ func(dest, src2, src1, tsz);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
+TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
+TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
+TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
+TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
+TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
+TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
+TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 574c055..66bc314 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -27,6 +27,7 @@
%si14 10:s14
%hint 0:5
%whint 0:15
+%code 0:15
#
# Argument sets
@@ -46,6 +47,8 @@
&fmt_rdrjsi14 rd rj si14
&fmt_hintrjsi12 hint rj si12
&fmt_whint whint
+&fmt_rjrk rj rk
+&fmt_code code
#
# Formats
@@ -65,6 +68,8 @@
@fmt_hintrjsi12 .... ...... ............ ..... ..... &fmt_hintrjsi12 %hint %rj %si12
@fmt_whint .... ........ ..... ............... &fmt_whint %whint
@fmt_rdrjsi14 .... .... .............. ..... ..... &fmt_rdrjsi14 %rd %rj %si14
+@fmt_rjrk .... ........ ..... ..... ..... ..... &fmt_rjrk %rj %rk
+@fmt_code .... ........ ..... ............... &fmt_code %code
#
# Fixed point arithmetic operation instruction
@@ -260,3 +265,23 @@ ammax_db_wu 0011 10000111 00000 ..... ..... ..... @fmt_rdrjrk
ammax_db_du 0011 10000111 00001 ..... ..... ..... @fmt_rdrjrk
ammin_db_wu 0011 10000111 00010 ..... ..... ..... @fmt_rdrjrk
ammin_db_du 0011 10000111 00011 ..... ..... ..... @fmt_rdrjrk
+
+#
+# Fixed point extra instruction
+#
+crc_w_b_w 0000 00000010 01000 ..... ..... ..... @fmt_rdrjrk
+crc_w_h_w 0000 00000010 01001 ..... ..... ..... @fmt_rdrjrk
+crc_w_w_w 0000 00000010 01010 ..... ..... ..... @fmt_rdrjrk
+crc_w_d_w 0000 00000010 01011 ..... ..... ..... @fmt_rdrjrk
+crcc_w_b_w 0000 00000010 01100 ..... ..... ..... @fmt_rdrjrk
+crcc_w_h_w 0000 00000010 01101 ..... ..... ..... @fmt_rdrjrk
+crcc_w_w_w 0000 00000010 01110 ..... ..... ..... @fmt_rdrjrk
+crcc_w_d_w 0000 00000010 01111 ..... ..... ..... @fmt_rdrjrk
+break 0000 00000010 10100 ............... @fmt_code
+syscall 0000 00000010 10110 ............... @fmt_code
+asrtle_d 0000 00000000 00010 ..... ..... 00000 @fmt_rjrk
+asrtgt_d 0000 00000000 00011 ..... ..... 00000 @fmt_rjrk
+rdtimel_w 0000 00000000 00000 11000 ..... ..... @fmt_rdrj
+rdtimeh_w 0000 00000000 00000 11001 ..... ..... @fmt_rdrj
+rdtime_d 0000 00000000 00000 11010 ..... ..... @fmt_rdrj
+cpucfg 0000 00000000 00000 11011 ..... ..... @fmt_rdrj
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index a4ffaf9..0a1a47b 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -14,6 +14,8 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "internals.h"
+#include "qemu/crc32c.h"
+#include <zlib.h>
/* Exceptions helpers */
void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
@@ -57,3 +59,27 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
do_raise_exception(env, EXCP_ADE, GETPC());
}
}
+
+target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
+{
+ uint8_t buf[8];
+ target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
+
+ m &= mask;
+ stq_le_p(buf, m);
+ return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
+}
+
+target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
+{
+ uint8_t buf[8];
+ target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
+ m &= mask;
+ stq_le_p(buf, m);
+ return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff);
+}
+
+target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj)
+{
+ return env->cpucfg[rj];
+}
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index a6482c3..77b0180 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -192,6 +192,7 @@ static bool gen_r3(DisasContext *ctx, arg_fmt_rdrjrk *a,
#include "insn_trans/trans_bit.c"
#include "insn_trans/trans_memory.c"
#include "insn_trans/trans_atomic.c"
+#include "insn_trans/trans_extra.c"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
1.8.3.1
next prev parent reply other threads:[~2021-08-27 7:55 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-27 7:14 [PATCH v3 00/19] Add LoongArch linux-user emulation support Song Gao
2021-08-27 7:14 ` [PATCH v3 01/19] target/loongarch: Add README Song Gao
2021-08-27 15:06 ` Peter Xu
2021-08-30 1:06 ` Song Gao
2021-08-27 7:14 ` [PATCH v3 02/19] target/loongarch: Add core definition Song Gao
2021-08-27 7:14 ` [PATCH v3 03/19] target/loongarch: Add main translation routines Song Gao
2021-08-27 7:14 ` [PATCH v3 04/19] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-08-27 7:14 ` [PATCH v3 05/19] target/loongarch: Add fixed point shift " Song Gao
2021-08-27 7:14 ` [PATCH v3 06/19] target/loongarch: Add fixed point bit " Song Gao
2021-08-27 7:14 ` [PATCH v3 07/19] target/loongarch: Add fixed point load/store " Song Gao
2021-08-27 7:14 ` [PATCH v3 08/19] target/loongarch: Add fixed point atomic " Song Gao
2021-08-27 7:14 ` Song Gao [this message]
2021-08-27 7:14 ` [PATCH v3 10/19] target/loongarch: Add floating point arithmetic " Song Gao
2021-08-27 7:14 ` [PATCH v3 11/19] target/loongarch: Add floating point comparison " Song Gao
2021-08-27 7:14 ` [PATCH v3 12/19] target/loongarch: Add floating point conversion " Song Gao
2021-08-27 7:14 ` [PATCH v3 13/19] target/loongarch: Add floating point move " Song Gao
2021-08-27 7:14 ` [PATCH v3 14/19] target/loongarch: Add floating point load/store " Song Gao
2021-08-27 7:14 ` [PATCH v3 15/19] target/loongarch: Add branch " Song Gao
2021-08-27 7:14 ` [PATCH v3 16/19] target/loongarch: Add disassembler Song Gao
2021-08-27 7:14 ` [PATCH v3 17/19] LoongArch Linux User Emulation Song Gao
2021-08-27 7:14 ` [PATCH v3 18/19] default-configs: Add loongarch linux-user support Song Gao
2021-08-27 7:14 ` [PATCH v3 19/19] target/loongarch: Add target build suport Song Gao
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