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Sat, 25 Jan 2025 09:36:37 -0800 (PST) Received: from [192.168.74.94] ([50.200.230.211]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21da414ed53sm34540875ad.203.2025.01.25.09.36.36 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jan 2025 09:36:36 -0800 (PST) Message-ID: <16467dca-39be-4a15-af00-a1729a76cdb5@linaro.org> Date: Sat, 25 Jan 2025 09:36:35 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 32/76] target/arm: Set up float_status to use for FPCR.AH=1 behaviour To: qemu-devel@nongnu.org References: <20250124162836.2332150-1-peter.maydell@linaro.org> <20250124162836.2332150-33-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250124162836.2332150-33-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/24/25 08:27, Peter Maydell wrote: > When FPCR.AH is 1, the behaviour of some instructions changes: > * AdvSIMD BFCVT, BFCVTN, BFCVTN2, BFMLALB, BFMLALT > * SVE BFCVT, BFCVTNT, BFMLALB, BFMLALT, BFMLSLB, BFMLSLT > * SME BFCVT, BFCVTN, BFMLAL, BFMLSL (these are all in SME2 which > QEMU does not yet implement) > * FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS > > The behaviour change is: > * the instructions do not update the FPSR cumulative exception flags > * trapped floating point exceptions are disabled (a no-op for QEMU, > which doesn't implement FPCR.{IDE,IXE,UFE,OFE,DZE,IOE}) > * rounding is always round-to-nearest-even regardless of FPCR.RMode > * denormalized inputs and outputs are always flushed to zero, as if > FPCR.{FZ,FIZ} is {1,1} > * FPCR.FZ16 is still honoured for half-precision inputs > > (See the Arm ARM DDI0487L.a section A1.5.9.) > > We can provide all these behaviours with another pair of float_status fields > which we use only for these insns, when FPCR.AH is 1. These float_status > fields will always have: > * flush_to_zero and flush_inputs_to_zero set for the non-F16 field > * rounding mode set to round-to-nearest-even > and so the only FPCR fields they need to honour are DN and FZ16. > > In this commit we only define the new fp_status fields and give them > the required behaviour when FPSR is updated. In subsequent commits > we will arrange to use this new fp_status field for the instructions > that should be affected by FPCR.AH in this way. > > Signed-off-by: Peter Maydell > --- > I'm not super enthusiastic about the ah_fp_status naming, which sort > of suggests it's always to be used when AH=1, rather than "for this > specific group of insns when AH=1". But I couldn't think of a better > name that was still reasonably short... > --- Hmm. I should really compare this vs the new pair of fp_status that I add for SME2, which also do not write back exception flags. Anyway, Reviewed-by: Richard Henderson r~