From: ~eopxd <eopxd@git.sr.ht>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: WeiWei Li <liweiwei@iscas.ac.cn>,
Frank Chang <frank.chang@sifive.com>,
eop Chen <eop.chen@sifive.com>, Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH qemu 4/9] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
Date: Thu, 17 Mar 2022 01:43:10 -0700 [thread overview]
Message-ID: <165089631935.4839.7564289944057093570-4@git.sr.ht> (raw)
In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht>
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index e2bdfc0fae..a085ef2c29 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1935,6 +1935,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 658ea0244d..269e40c251 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1291,10 +1291,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t esz = sizeof(TS1); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, \
+ (i + 1) * esz); \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1332,10 +1336,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t esz = sizeof(TD); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, \
+ i * esz, \
+ (i + 1) * esz);\
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
--
2.34.2
next prev parent reply other threads:[~2022-04-25 14:25 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-25 14:18 [PATCH qemu 0/9] Add mask agnostic behavior for rvv instructions ~eopxd
2022-03-17 7:26 ` [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions ~eopxd
2022-04-26 8:47 ` Weiwei Li
2022-04-26 18:20 ` eop Chen
2022-04-27 1:01 ` Weiwei Li
2022-04-27 2:07 ` eop Chen
2022-04-27 3:27 ` Weiwei Li
2022-04-27 3:43 ` eop Chen
2022-03-17 7:47 ` [PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions ~eopxd
2022-03-17 8:38 ` [PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions ~eopxd
2022-03-17 8:43 ` ~eopxd [this message]
2022-03-17 8:46 ` [PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions ~eopxd
2022-03-17 8:52 ` [PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions ~eopxd
2022-03-17 9:08 ` [PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions ~eopxd
2022-03-17 9:14 ` [PATCH qemu 8/9] target/riscv: rvv: Add mask agnostic for vector mask instructions ~eopxd
2022-03-17 9:32 ` [PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions ~eopxd
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