From: liweiwei <liweiwei@iscas.ac.cn>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: liweiwei@iscas.ac.cn, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch
Date: Tue, 28 Mar 2023 12:09:40 +0800 [thread overview]
Message-ID: <165c20a1-222a-9b75-c23a-10bbc0619c65@iscas.ac.cn> (raw)
In-Reply-To: <aa9b6745-341f-2466-70c2-d574ce2a7c6a@linaro.org>
On 2023/3/28 11:31, Richard Henderson wrote:
> On 3/27/23 18:55, liweiwei wrote:
>>
>> On 2023/3/28 02:04, Richard Henderson wrote:
>>> On 3/27/23 03:00, Weiwei Li wrote:
>>>> @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
>>>> address, int size,
>>>> qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d
>>>> mmu_idx %d\n",
>>>> __func__, address, access_type, mmu_idx);
>>>> + if (access_type == MMU_INST_FETCH) {
>>>> + address = adjust_pc_address(env, address);
>>>> + }
>>>
>>> Why do you want to do this so late, as opposed to earlier in
>>> cpu_get_tb_cpu_state?
>>
>> In this way, the pc for tb may be different from the reg pc. Then the
>> pc register will be wrong if sync from tb.
>
> Hmm, true.
>
> But you certainly cannot adjust the address in tlb_fill, as you'll be
> producing different result for read/write and exec. You could
> plausibly use a separate mmu_idx, but that's not ideal either.
>
> The best solution might be to implement pc-relative translation
> (CF_PCREL). At which point cpu_pc always has the correct results and
> we make relative adjustments to that.
I'm not very familiar with how CF_PCREL works currently. I'll try this
way later.
Regards,
Weiwei Li
>
>
> r~
prev parent reply other threads:[~2023-03-28 4:10 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 10:00 [PATCH 0/5] target/riscv: Fix pointer mask related support Weiwei Li
2023-03-27 10:00 ` [PATCH 1/5] target/riscv: Fix effective address for pointer mask Weiwei Li
2023-03-27 13:19 ` Daniel Henrique Barboza
2023-03-28 2:20 ` LIU Zhiwei
2023-03-28 2:48 ` liweiwei
2023-03-28 3:18 ` Richard Henderson
2023-03-28 3:24 ` LIU Zhiwei
2023-03-28 3:33 ` liweiwei
2023-03-28 7:25 ` LIU Zhiwei
2023-03-28 10:26 ` liweiwei
2023-03-27 10:00 ` [PATCH 2/5] target/riscv: Use sign-extended data address when xl = 32 Weiwei Li
2023-03-27 13:20 ` Daniel Henrique Barboza
2023-03-28 2:14 ` LIU Zhiwei
2023-03-28 3:07 ` liweiwei
2023-03-27 10:00 ` [PATCH 3/5] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-03-27 13:20 ` Daniel Henrique Barboza
2023-03-28 2:21 ` LIU Zhiwei
2023-03-27 10:00 ` [PATCH 4/5] target/riscv: take xl into consideration " Weiwei Li
2023-03-27 13:21 ` Daniel Henrique Barboza
2023-03-28 2:21 ` LIU Zhiwei
2023-03-27 10:00 ` [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
2023-03-27 13:28 ` Daniel Henrique Barboza
2023-03-27 15:13 ` Daniel Henrique Barboza
2023-03-27 18:04 ` Richard Henderson
2023-03-28 1:55 ` liweiwei
2023-03-28 2:31 ` LIU Zhiwei
2023-03-28 3:14 ` liweiwei
2023-03-28 3:31 ` Richard Henderson
2023-03-28 4:09 ` liweiwei [this message]
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