From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Andrew Jeffery <andrew@aj.id.au>, qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com,
minyard@acm.org, qemu-devel@nongnu.org, joel@jms.id.au,
clg@kaod.org
Subject: Re: [PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC
Date: Fri, 26 Feb 2021 09:56:34 +0100 [thread overview]
Message-ID: <1681fdc1-2c9d-db2c-a872-c0ff156e07c4@amsat.org> (raw)
In-Reply-To: <20210226065758.547824-2-andrew@aj.id.au>
On 2/26/21 7:57 AM, Andrew Jeffery wrote:
> This appears to be a requirement of the GIC model.
If so this should be adjusted in the GIC or a15mp_priv_realize(),
not in each caller, isn't it?
> The AST2600 allocates
> 197 GIC IRQs, which we will adjust shortly.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> hw/arm/aspeed_ast2600.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
next prev parent reply other threads:[~2021-02-26 8:58 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-26 6:57 [PATCH 0/4] aspeed: LPC peripheral controller devices Andrew Jeffery
2021-02-26 6:57 ` [PATCH 1/4] arm: ast2600: Force a multiple of 32 of IRQs for the GIC Andrew Jeffery
2021-02-26 8:56 ` Philippe Mathieu-Daudé [this message]
2021-02-28 23:07 ` Andrew Jeffery
2021-03-01 0:23 ` Andrew Jeffery
2021-02-26 6:57 ` [PATCH 2/4] arm: ast2600: Fix iBT IRQ ID Andrew Jeffery
2021-02-26 8:58 ` Philippe Mathieu-Daudé
2021-02-28 23:08 ` Andrew Jeffery
2021-02-26 6:57 ` [PATCH 3/4] hw/misc: Add a basic Aspeed LPC controller model Andrew Jeffery
2021-02-26 6:57 ` [PATCH 4/4] hw/misc: Model KCS devices in the Aspeed LPC controller Andrew Jeffery
2021-02-26 9:51 ` Cédric Le Goater
2021-02-28 23:14 ` Andrew Jeffery
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