Qemu MIPSel -- MIPS32R1 Config1 register wrong.

[Traveler <travellernmri@gmail.com>]

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Hello Qemu community,

Today I used Qemu to simulate a mipssim machine, which is equipped with a 4K mipsel CPU (MIPS32R1). When I used gdb-multiarch to debug my Linux kernel, I found that the config1 register of coprocessor 0 had a bit error. Whenever the config1 register (i.e., selection 1 of the config register) is always 0, this should be different from the 31st bit of the config0 register. I flipped through the MIPS32® 4KTM Processor Core Family Software User’s Manual Revision 01.18 and found an explanation on page 98 of the manual. "This bit is hardwired to '0' to indicate the absence of the Config2 register." The value of the config1 register of the qemu virtual machine at startup is 0x9e190c8a. Obviously, the 31st bit of config1 is set to 1 by mistake.

Although this may not cause a big impact, some operating system developers *may* rely on this property of mips32 to verify whether the cpu is valid.

I'm glad to hear from you.


Best regards,
TravelerPaws

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