From: David Hildenbrand <david@redhat.com>
To: Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org
Cc: thuth@redhat.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU
Date: Tue, 20 Jun 2017 10:12:43 +0200 [thread overview]
Message-ID: <169e898c-98f6-a6d6-7045-1b2606469fe4@redhat.com> (raw)
In-Reply-To: <20170620000405.3391-16-rth@twiddle.net>
> +uint64_t HELPER(srstu)(CPUS390XState *env, uint64_t end, uint64_t str)
> +{
> + uintptr_t ra = GETPC();
> + uint32_t len;
> + uint16_t v, c = env->regs[0];
> + uint64_t adj_end;
> +
> + /* Bits 32-47 of R0 must be zero. */
> + if (env->regs[0] & 0xffff0000u) {
> + cpu_restore_state(ENV_GET_CPU(env), ra);
> + program_interrupt(env, PGM_SPECIFICATION, 6);
> + }
> +
> + str = wrap_address(env, str);
> + end = wrap_address(env, end);
> +
> + /* If the LSB of the two addresses differ, use one extra byte. */
> + adj_end = end + ((str ^ end) & 1);
This could theoretically wrap. Not sure how this is to be handled, do you?
> +
> + /* Assume for now that R2 is unmodified. */
> + env->retxl = str;
If str was wrapped, r2 could be modified although it should not be touched.
> +
> + /* Lest we fail to service interrupts in a timely manner, limit the
> + amount of work we're willing to do. For now, let's cap at 8k. */
> + for (len = 0; len < 0x2000; len += 2) {
> + if (str + len == adj_end) {
> + /* End of input found. */
> + env->cc_op = 2;
> + return end;
If end was wrapped, r1 is modified here.
> + }
Also str + len could wrap here. Not sure how this is to be handled.
> + v = cpu_lduw_data_ra(env, str + len, ra);
> + if (v == c) {
> + /* Character found. Set R1 to the location; R2 is unmodified. */
> + env->cc_op = 1;
> + return str + len;
> + }
> + }
> +
> + /* CPU-determined bytes processed. Advance R2 to next byte to process. */
> + env->retxl = str + len;
Also wonder if r2 should be wrapped here. And if the "unused" bits
should be left unmodified here.
> + env->cc_op = 3;
> + return end;
Again, r1 could be modified here if end was wrapped.
> +}
> +
> /* unsigned string compare (c is string terminator) */
> uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2)
> {
> diff --git a/target/s390x/translate.c b/target/s390x/translate.c
> index 4a860f1..e594b91 100644
> --- a/target/s390x/translate.c
> +++ b/target/s390x/translate.c
> @@ -4262,6 +4262,14 @@ static ExitStatus op_srst(DisasContext *s, DisasOps *o)
> return NO_EXIT;
> }
>
> +static ExitStatus op_srstu(DisasContext *s, DisasOps *o)
> +{
> + gen_helper_srstu(o->in1, cpu_env, o->in1, o->in2);
> + set_cc_static(s);
> + return_low128(o->in2);
> + return NO_EXIT;
> +}
> +
> static ExitStatus op_sub(DisasContext *s, DisasOps *o)
> {
> tcg_gen_sub_i64(o->out, o->in1, o->in2);
>
Apart from special wrapping conditions, looks good to me!
(will scan the PoP how wrapping is to be handled in general during an
instruction. Some (like mvcos) mention it explicitly, others don't)
--
Thanks,
David
next prev parent reply other threads:[~2017-06-20 8:12 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-20 0:03 [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 01/18] target/s390x: Map existing FAC_* names to S390_FEAT_* names Richard Henderson
2017-06-23 10:58 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 02/18] target/s390x: change PSW_SHIFT_KEY Richard Henderson
2017-06-23 10:59 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 03/18] target/s390x: implement mvcos instruction Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 04/18] target/s390x: Implement CSST Richard Henderson
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 05/18] target/s390x: Mark FPSEH facility as available Richard Henderson
2017-06-23 10:59 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 06/18] target/s390x: Implement load-on-condition-2 insns Richard Henderson
2017-06-23 11:00 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 08/18] target/s390x: Mark STFLE_53 facility as available Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 10/18] target/s390x: Implement processor-assist insn Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 11/18] target/s390x: Mark STFLE_49 facility as available Richard Henderson
2017-06-23 11:01 ` Aurelien Jarno
2017-06-20 0:03 ` [Qemu-devel] [PATCH v3 12/18] target/s390x: Finish implementing ETF2-ENH Richard Henderson
2017-06-23 11:02 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 13/18] target/s390x: Implement CONVERT UNICODE insns Richard Henderson
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 14/18] target/s390x: Tidy SRST Richard Henderson
2017-06-20 7:33 ` David Hildenbrand
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 15/18] target/s390x: Implement SRSTU Richard Henderson
2017-06-20 8:12 ` David Hildenbrand [this message]
2017-06-20 8:27 ` David Hildenbrand
2017-06-20 17:21 ` Richard Henderson
2017-06-23 15:52 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 16/18] target/s390x: Implement TRTR Richard Henderson
2017-06-23 15:53 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 17/18] target/s390x: Mark ETF3 and ETF3_ENH facilities as available Richard Henderson
2017-06-23 15:53 ` Aurelien Jarno
2017-06-20 0:04 ` [Qemu-devel] [PATCH v3 18/18] target/s390x: Clean up TB flag bits Richard Henderson
2017-06-20 3:16 ` Philippe Mathieu-Daudé
2017-06-23 15:53 ` Aurelien Jarno
[not found] ` <20170620000405.3391-8-rth@twiddle.net>
2017-06-23 11:01 ` [Qemu-devel] [PATCH v3 07/18] target/s390x: Implement load-and-zero-rightmost-byte insns Aurelien Jarno
[not found] ` <20170620000405.3391-10-rth@twiddle.net>
2017-06-23 11:01 ` [Qemu-devel] [PATCH v3 09/18] target/s390x: Implement execution-hint insns Aurelien Jarno
2017-06-23 16:05 ` [Qemu-devel] [PATCH v3 00/18] target/s390x improvements Aurelien Jarno
2017-06-27 15:54 ` David Hildenbrand
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