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Thu, 29 Aug 2024 20:35:27 +0000 (GMT) Message-ID: <16bbfc74-e7c0-41b6-a91f-c2d121296986@linux.ibm.com> Date: Thu, 29 Aug 2024 15:35:26 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 11/13] pnv/xive: Update PIPR when updating CPPR To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, milesg@linux.ibm.com References: <20240801203008.11224-1-kowal@linux.ibm.com> <20240801203008.11224-12-kowal@linux.ibm.com> <5dad962a-0815-40b8-b62a-d0c67612fa5f@kaod.org> Content-Language: en-US From: Mike Kowal In-Reply-To: <5dad962a-0815-40b8-b62a-d0c67612fa5f@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: ZSxLouGNB5m6k7mD-Z_2haE8nEyEEuxY X-Proofpoint-ORIG-GUID: WxKxIaCw2vc6EZF4qG1AFA4sRsjEjOqv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_06,2024-08-29_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 impostorscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290145 Received-SPF: pass client-ip=148.163.156.1; envelope-from=kowal@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/29/2024 7:29 AM, Cédric Le Goater wrote: > On 8/1/24 22:30, Michael Kowal wrote: >> From: Glenn Miles >> >> Current code was updating the PIPR inside the xive_tctx_accept() >> function >> instead of the xive_tctx_set_cppr function, which is where the HW would >> have it updated. > > Did you confirm with the HW designer ? > > AFAIR, the PIPR is constructed from the IPB and the later is it updated > the better. However, if now, both PIPR (HW and Pool) are required to > identify the ctx to notify, I agree set_cppr() needs a change but what > about xive_tctx_ipb_update() which is called when an interrupt > needs a resend ? This was fix to a bug and matches what  is specified in the XIVE2 architecture document CPPR flows (MMIO CPPR xxx processing). > > > Thanks, > > C. > > > >> Moved the update to the xive_tctx_set_cppr function which required >> additional support for pool interrupts. >> >> Signed-off-by: Glenn Miles >> Signed-off-by: Michael Kowal >> --- >>   hw/intc/xive.c | 34 ++++++++++++++++++++++++++++++++-- >>   1 file changed, 32 insertions(+), 2 deletions(-) >> >> diff --git a/hw/intc/xive.c b/hw/intc/xive.c >> index 5c4ca7f6e0..d951aac3a0 100644 >> --- a/hw/intc/xive.c >> +++ b/hw/intc/xive.c >> @@ -89,7 +89,6 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, >> uint8_t ring) >>             /* Reset the pending buffer bit */ >>           aregs[TM_IPB] &= ~xive_priority_to_ipb(cppr); >> -        regs[TM_PIPR] = ipb_to_pipr(aregs[TM_IPB]); >>             /* Drop Exception bit */ >>           regs[TM_NSR] &= ~mask; >> @@ -143,6 +142,8 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, >> uint8_t ring) >>   static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, >> uint8_t cppr) >>   { >>       uint8_t *regs = &tctx->regs[ring]; >> +    uint8_t pipr_min; >> +    uint8_t ring_min; >>         trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, >>                                regs[TM_IPB], regs[TM_PIPR], >> @@ -154,8 +155,37 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, >> uint8_t ring, uint8_t cppr) >>         tctx->regs[ring + TM_CPPR] = cppr; >>   +    /* >> +     * Recompute the PIPR based on local pending interrupts. The PHYS >> +     * ring must take the minimum of both the PHYS and POOL PIPR >> values. >> +     */ >> +    pipr_min = ipb_to_pipr(regs[TM_IPB]); >> +    ring_min = ring; >> + >> +    /* PHYS updates also depend on POOL values */ >> +    if (ring == TM_QW3_HV_PHYS) { >> +        uint8_t *pregs = &tctx->regs[TM_QW2_HV_POOL]; >> + >> +        /* POOL values only matter if POOL ctx is valid */ >> +        if (pregs[TM_WORD2] & 0x80) { >> + >> +            uint8_t pool_pipr = ipb_to_pipr(pregs[TM_IPB]); >> + >> +            /* >> +             * Determine highest priority interrupt and >> +             * remember which ring has it. >> +             */ >> +            if (pool_pipr < pipr_min) { >> +                pipr_min = pool_pipr; >> +                ring_min = TM_QW2_HV_POOL; >> +            } >> +        } >> +    } >> + >> +    regs[TM_PIPR] = pipr_min; >> + >>       /* CPPR has changed, check if we need to raise a pending >> exception */ >> -    xive_tctx_notify(tctx, ring); >> +    xive_tctx_notify(tctx, ring_min); >>   } >>     void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb) >