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Tue, 02 Apr 2024 06:26:27 -0700 (PDT) Message-ID: <16cb6ac0-818b-4393-8b27-20879a150a79@linaro.org> Date: Tue, 2 Apr 2024 15:26:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] sh4: mac.w: memory accesses are 16-bit words To: Zack Buhman , qemu-devel@nongnu.org References: <20240402093756.27466-1-zack@buhman.org> Content-Language: en-US Cc: Samuel Tardieu , Aurelien Jarno , Yoshinori Sato From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240402093756.27466-1-zack@buhman.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/4/24 11:37, Zack Buhman wrote: > Before this change, executing a code sequence such as: > > mova tblm,r0 > mov r0,r1 > mova tbln,r0 > clrs > clrmac > mac.w @r0+,@r1+ > mac.w @r0+,@r1+ > > .align 4 > tblm: .word 0x1234 > .word 0x5678 > tbln: .word 0x9abc > .word 0xdefg > > Does not result in correct behavior: > > Expected behavior: > first macw : macl = 0x1234 * 0x9abc + 0x0 > mach = 0x0 > > second macw: macl = 0x5678 * 0xdefg + 0xb00a630 > mach = 0x0 > > Observed behavior (qemu-sh4eb, prior to this commit): > > first macw : macl = 0x5678 * 0xdefg + 0x0 > mach = 0x0 > > second macw: (unaligned longword memory access, SIGBUS) > > Various SH-4 ISA manuals also confirm that `mac.w` is a 16-bit word memory > access, not a 32-bit longword memory access. > > Signed-off-by: Zack Buhman > --- > target/sh4/translate.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/sh4/translate.c b/target/sh4/translate.c > index a9b1bc7524..6643c14dde 100644 > --- a/target/sh4/translate.c > +++ b/target/sh4/translate.c > @@ -816,10 +816,10 @@ static void _decode_opc(DisasContext * ctx) > TCGv arg0, arg1; > arg0 = tcg_temp_new(); > tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, > - MO_TESL | MO_ALIGN); > + MO_TESW | MO_ALIGN); > arg1 = tcg_temp_new(); > tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, > - MO_TESL | MO_ALIGN); > + MO_TESW | MO_ALIGN); Apparently invalid since its introduction in commit fdf9b3e831. Reviewed-by: Philippe Mathieu-Daudé > gen_helper_macw(tcg_env, arg0, arg1); > tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); > tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);