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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id n14sm35766786wra.75.2019.06.26.00.45.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 00:45:38 -0700 (PDT) To: Mark Cave-Ayland , Aleksandar Markovic References: <20190519041522.12327-1-richard.henderson@linaro.org> <8f28d008-2608-a579-7505-4546b08deb41@linaro.org> <085d6881-f518-9888-a13e-081cdc09de46@ilande.co.uk> <0b9f4772-37f6-1453-e4ea-5ad9d0f52a5b@ilande.co.uk> <68facefc-b801-4902-11c0-4542662bfc4e@linaro.org> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <16f26b7f-2435-aa05-66a3-073e8310d5c8@linaro.org> Date: Wed, 26 Jun 2019 09:45:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: Re: [Qemu-devel] [PATCH v4 0/7] tcg/ppc: Add vector opcodes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Howard Spoelstra , QEMU Developers , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/25/19 7:55 PM, Mark Cave-Ayland wrote: > And here's where we are blowing up according to -d in_asm,op_out_asm: > > IN: > 0x00f22ca0: 101ffc84 vor v0, v31, v31 > > OP: > ld_i32 tmp0,env,$0xfffffff8 > movi_i32 tmp1,$0x0 > brcond_i32 tmp0,tmp1,lt,$L0 > > ---- 00f22ca0 > ld_vec v128,e8,tmp2,env,$0xd6b0 > st_vec v128,e8,tmp2,env,$0xd4c0 Yep, that looks right. As an aside, this does suggest to me that target/ppc might be well served in moving the ppc_vsr_t members of CPUPPCState earlier, so that this offset is smaller. > movi_i32 nip,$0xf22ca4 > movi_i32 nip,$0xf22ca4 > movi_i32 tmp0,$0x10002 > call raise_exception,$0x2,$0,env,tmp0 And this, presumably is the single-step debug exception. > 0xa4e7f12c: 3c400000 lis r2, 0 > 0xa4e7f130: 6042d6b0 ori r2, r2, 0xd6b0 > 0xa4e7f134: 7c5b10ce lvx v2, r27, r2 > 0xa4e7f138: 3c400000 lis r2, 0 > 0xa4e7f13c: 6042d4c0 ori r2, r2, 0xd4c0 > 0xa4e7f140: 7c5b11ce stvx v2, r27, r2 These also look correct. Form an offset into r2, load or store from env+r2. This also shows what I mention above re offset. For a ppc host, the offset is large enough to require two instructions to form them. > Any ideas what might be going on here? What is the observed problem that makes you think that this is the incorrect instruction? r~