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([2602:ae:1598:4c01:66a6:82c2:d794:68f6]) by smtp.gmail.com with ESMTPSA id ik8-20020a170902ab0800b001a194df5a58sm2345266plb.167.2023.06.02.22.55.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Jun 2023 22:55:41 -0700 (PDT) Message-ID: <16f864db-7f60-3176-461d-f510243d2d60@linaro.org> Date: Fri, 2 Jun 2023 22:55:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 04/20] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20230602155223.2040685-1-peter.maydell@linaro.org> <20230602155223.2040685-5-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20230602155223.2040685-5-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.095, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/2/23 08:52, Peter Maydell wrote: > Convert the CFINV, XAFLAG and AXFLAG insns to decodetree. > The old decoder handles these in handle_msr_i(), but > the architecture defines them as separate instructions > from MSR (immediate). > > Signed-off-by: Peter Maydell > --- > target/arm/tcg/a64.decode | 6 ++++ > target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++---------------- > 2 files changed, 35 insertions(+), 27 deletions(-) > > diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode > index 553f6904d9c..26a0b44cea9 100644 > --- a/target/arm/tcg/a64.decode > +++ b/target/arm/tcg/a64.decode > @@ -188,3 +188,9 @@ CLREX 1101 0101 0000 0011 0011 imm:4 010 11111 > DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 > ISB 1101 0101 0000 0011 0011 imm:4 110 11111 > SB 1101 0101 0000 0011 0011 0000 111 11111 > + > +# PSTATE > + > +CFINV 1101 0101 0000 0 000 0100 0000 000 11111 > +XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 > +AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 > diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c > index 09258a9854f..33bebe594d1 100644 > --- a/target/arm/tcg/translate-a64.c > +++ b/target/arm/tcg/translate-a64.c > @@ -1809,9 +1809,25 @@ static bool trans_SB(DisasContext *s, arg_SB *a) > return true; > } > > -static void gen_xaflag(void) > +static bool trans_CFINV(DisasContext *s, arg_CFINV *a) > { > - TCGv_i32 z = tcg_temp_new_i32(); > + if (!dc_isar_feature(aa64_condm_4, s)) { > + return false; > + } > + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); > + s->base.is_jmp = DISAS_NEXT; > + return true; > +} The settings of is_jmp do not need to be copied across. That's another benefit of extracting from MSR_i. Otherwise, Reviewed-by: Richard Henderson r~