Re: [PATCH 2/2] target/arm/translate-neon: Simplify align field check for VLD3

[Richard Henderson <richard.henderson@linaro.org>]

On 3/3/22 01:37, Peter Maydell wrote:
> For VLD3 (single 3-element structure to one lane), there is no
> alignment specification and the alignment bits in the instruction
> must be zero.  This is bit [4] for the size=0 and size=1 cases, and
> bits [5:4] for the size=2 case.  We do this check correctly in
> VLDST_single(), but we write it a bit oddly: in the 'case 3' code we
> check for bit 0 of a->align (bit [4] of the insn), and then we fall
> through to the 'case 2' code which checks bit 1 of a->align (bit [5]
> of the insn) in the size 2 case.  Replace this with just checking "is
> a->align non-zero" for VLD3, which lets us drop the fall-through and
> put the cases in this switch in numerical order.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   target/arm/translate-neon.c | 10 +++++-----
>   1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>

r~