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([2602:ae:154e:c001:caf5:5ae2:432a:1bdf]) by smtp.gmail.com with ESMTPSA id r6-20020a17090b050600b00263f8915aa3sm3048131pjz.31.2023.07.27.10.56.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jul 2023 10:56:33 -0700 (PDT) Message-ID: <173fb35e-a4c3-4112-afd9-b313c6d95b2e@linaro.org> Date: Thu, 27 Jul 2023 10:56:31 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [RFC PATCH] target/i386: Truncate ESP when exiting from long mode Content-Language: en-US From: Richard Henderson To: Ard Biesheuvel , qemu-devel@nongnu.org Cc: Paolo Bonzini , Eduardo Habkost References: <20230726081710.1051126-1-ardb@kernel.org> <67a8967e-338a-fbd1-1c06-d5a35f2db509@linaro.org> In-Reply-To: <67a8967e-338a-fbd1-1c06-d5a35f2db509@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/26/23 08:01, Richard Henderson wrote: > On 7/26/23 01:17, Ard Biesheuvel wrote: >> Hints welcome on where the architectural behavior is specified, and in particular, >> whether or not other 64-bit GPRs can be relied upon to preserve their full 64-bit >> length values. > > No idea about chapter and verse, but it has the feel of being part and parcel with the > truncation of eip.  While esp is always special, I suspect that none of the GPRs can be > relied on carrying all bits. Coincidentally, I was having a gander at the newly announced APX extension [1], and happened across 3.1.4.1.2 Extended GPR Access (Direct and Indirect) ... Entering/leaving 64-bit mode via traditional (explicit) control flow does not directly alter the content of the EGPRs (EGPRs behave similar to R8-R15 in this regard). which suggests to me that the 8 low registers are squashed to 32-bit on transition to 32-bit IA-32e mode. I still have not found similar language in the main architecture manual. r~ [1] https://www.intel.com/content/www/us/en/content-details/784266/intel-advanced-performance-extensions-intel-apx-architecture-specification.html