From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ba4Xh-0008AW-6p for qemu-devel@nongnu.org; Wed, 17 Aug 2016 13:22:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ba4Xd-0007tP-0h for qemu-devel@nongnu.org; Wed, 17 Aug 2016 13:22:16 -0400 Received: from mail-qk0-x244.google.com ([2607:f8b0:400d:c09::244]:35218) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ba4Xc-0007tF-So for qemu-devel@nongnu.org; Wed, 17 Aug 2016 13:22:12 -0400 Received: by mail-qk0-x244.google.com with SMTP id o1so10646633qkd.2 for ; Wed, 17 Aug 2016 10:22:12 -0700 (PDT) Sender: Richard Henderson References: <87mvkeqph3.fsf@linaro.org> <20160815154626.GA8768@flamenco> <20160815154940.GA11939@flamenco> From: Richard Henderson Message-ID: <17473d21-f53e-b46f-8882-4b54b6444bc4@twiddle.net> Date: Wed, 17 Aug 2016 10:22:05 -0700 MIME-Version: 1.0 In-Reply-To: <20160815154940.GA11939@flamenco> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] aarch64: use TSX for ldrex/strex List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Emilio G. Cota" , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: mttcg@greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, mark.burton@greensocs.com, pbonzini@redhat.com, jan.kiszka@siemens.com, serge.fdrv@gmail.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, "Dr. David Alan Gilbert" , Peter Crosthwaite On 08/15/2016 08:49 AM, Emilio G. Cota wrote: > +void HELPER(xbegin)(CPUARMState *env) > +{ > + uintptr_t ra = GETPC(); > + int status; > + int retries = 100; > + > + retry: > + status = _xbegin(); > + if (status != _XBEGIN_STARTED) { > + if (status && retries) { > + retries--; > + goto retry; > + } > + if (parallel_cpus) { > + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); > + } > + } > +} > + > +void HELPER(xend)(void) > +{ > + if (_xtest()) { > + _xend(); > + } else { > + assert(!parallel_cpus); > + parallel_cpus = true; > + } > +} > + Interesting idea. FWIW, there are two other extant HTM implementations: ppc64 and s390x. As I recall, the s390 (but not the ppc64) transactions do not roll back the fp registers. Which suggests that we need special support within the TCG proglogue. Perhaps folding these operations into special TCG opcodes. I believe that power8 has HTM, and there's one of those in the gcc compile farm, so this should be relatively easy to try out. We increase the chances of success of the transaction if we minimize the amount of non-target code that's executed while the transaction is running. That suggests two things: (1) that it would be doubly helpful to incorporate the transaction start directly into TCG code generation rather than as a helper and (2) that we should start a new TB upon encountering a load-exclusive, so that we maximize the chance of the store-exclusive being a part of the same TB and thus have *nothing* extra between the beginning and commit of the transaction. r~