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[46.114.109.147]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb4982b30sm53309035e9.6.2025.10.10.09.38.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Oct 2025 09:38:48 -0700 (PDT) Message-ID: <174e2a19-85f4-48f5-9a22-aadd8c3848a6@canonical.com> Date: Fri, 10 Oct 2025 18:38:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 13/13] target/riscv: Introduce mo_endian_env() helper To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Cc: Christoph Muellner , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Richard Henderson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza , qemu-devel@nongnu.org, Ben Dooks References: <20251010155045.78220-1-philmd@linaro.org> <20251010155045.78220-14-philmd@linaro.org> Content-Language: en-US From: Heinrich Schuchardt In-Reply-To: <20251010155045.78220-14-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=185.125.188.122; envelope-from=heinrich.schuchardt@canonical.com; helo=smtp-relay-internal-0.canonical.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.441, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/10/25 17:50, Philippe Mathieu-Daudé wrote: > mo_endian_env() returns the target endianness from CPUArchState. > > Signed-off-by: Philippe Mathieu-Daudé LGTM Reviewed-by: Heinrich Schuchardt > --- > target/riscv/op_helper.c | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index c486f771d35..9d048089e2a 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -28,6 +28,18 @@ > #include "exec/tlb-flags.h" > #include "trace.h" > > +static inline MemOp mo_endian_env(CPURISCVState *env) > +{ > + /* > + * A couple of bits in MSTATUS set the endianness: > + * - MSTATUS_UBE (User-mode), > + * - MSTATUS_SBE (Supervisor-mode), > + * - MSTATUS_MBE (Machine-mode) > + * but we don't implement that yet. > + */ > + return MO_TE; > +} > + > /* Exceptions processing helpers */ > G_NORETURN void riscv_raise_exception(CPURISCVState *env, > RISCVException exception, > @@ -633,7 +645,7 @@ target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, false, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UW, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); > > return cpu_ldw_mmu(env, adjust_addr_virt(env, addr), oi, ra); > } > @@ -642,7 +654,7 @@ target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, false, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UL, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); > > return cpu_ldl_mmu(env, adjust_addr_virt(env, addr), oi, ra); > } > @@ -651,7 +663,7 @@ target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, false, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UQ, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UQ, mmu_idx); > > return cpu_ldq_mmu(env, adjust_addr_virt(env, addr), oi, ra); > } > @@ -669,7 +681,7 @@ void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong val) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, false, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UW, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); > > cpu_stw_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); > } > @@ -678,7 +690,7 @@ void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong val) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, false, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UL, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); > > cpu_stl_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); > } > @@ -687,7 +699,7 @@ void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong val) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, false, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UQ, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UQ, mmu_idx); > > cpu_stq_mmu(env, adjust_addr_virt(env, addr), val, oi, ra); > } > @@ -703,7 +715,7 @@ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, true, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UW, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UW, mmu_idx); > > return cpu_ldw_code_mmu(env, addr, oi, GETPC()); > } > @@ -712,7 +724,7 @@ target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr) > { > uintptr_t ra = GETPC(); > int mmu_idx = check_access_hlsv(env, true, ra); > - MemOpIdx oi = make_memop_idx(MO_TE | MO_UL, mmu_idx); > + MemOpIdx oi = make_memop_idx(mo_endian_env(env) | MO_UL, mmu_idx); > > return cpu_ldl_code_mmu(env, addr, oi, ra); > }