From: Paolo Savini <paolo.savini@embecosm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Helene Chelin <helene.chelin@embecosm.com>,
Max Chou <max.chou@sifive.com>
Subject: Re: [RFC 2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts of data.
Date: Tue, 10 Sep 2024 12:20:16 +0100 [thread overview]
Message-ID: <1753bd69-6f7a-4b34-a7ae-8a0b225b72c9@embecosm.com> (raw)
In-Reply-To: <8e0c2afd-4c31-47f8-ade9-60a83ca20859@linaro.org>
Thanks for the feedback Richard, I'm working on the endianness. Could
you please give me more details about the atomicity issues you are
referring to?
Best wishes
Paolo
On 7/27/24 08:15, Richard Henderson wrote:
> On 7/18/24 01:30, Paolo Savini wrote:
>> This patch optimizes the emulation of unit-stride load/store RVV
>> instructions
>> when the data being loaded/stored per iteration amounts to 64 bytes
>> or more.
>> The optimization consists of calling __builtin_memcpy on chunks of
>> data of 128
>> and 256 bytes between the memory address of the simulated vector
>> register and
>> the destination memory address and vice versa.
>> This is done only if we have direct access to the RAM of the host
>> machine.
>>
>> Signed-off-by: Paolo Savini <paolo.savini@embecosm.com>
>> ---
>> target/riscv/vector_helper.c | 17 ++++++++++++++++-
>> 1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
>> index 4b444c6bc5..7674972784 100644
>> --- a/target/riscv/vector_helper.c
>> +++ b/target/riscv/vector_helper.c
>> @@ -486,7 +486,22 @@ vext_group_ldst_host(CPURISCVState *env, void
>> *vd, uint32_t byte_end,
>> }
>> fn = fns[is_load][group_size];
>> - fn(vd, byte_offset, host + byte_offset);
>> +
>> + if (byte_offset + 32 < byte_end) {
>> + group_size = MO_256;
>> + if (is_load)
>> + __builtin_memcpy((uint8_t *)(vd + byte_offset), (uint8_t
>> *)(host + byte_offset), 32);
>> + else
>> + __builtin_memcpy((uint8_t *)(host + byte_offset), (uint8_t
>> *)(vd + byte_offset), 32);
>> + } else if (byte_offset + 16 < byte_end) {
>> + group_size = MO_128;
>> + if (is_load)
>> + __builtin_memcpy((uint8_t *)(vd + byte_offset), (uint8_t
>> *)(host + byte_offset), 16);
>> + else
>> + __builtin_memcpy((uint8_t *)(host + byte_offset), (uint8_t
>> *)(vd + byte_offset), 16);
>> + } else {
>> + fn(vd, byte_offset, host + byte_offset);
>> + }
>
> This will not work for big-endian hosts.
>
> This may have atomicity issues, depending on the spec, the compiler
> options, and the host capabilities.
>
>
> r~
>
next prev parent reply other threads:[~2024-09-10 11:20 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-17 15:30 [RFC 0/2] Improve the performance of unit-stride RVV ld/st on Paolo Savini
2024-07-17 15:30 ` [RFC 1/2] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores Paolo Savini
2024-07-26 12:22 ` Daniel Henrique Barboza
2024-07-27 7:13 ` Richard Henderson
2024-07-31 12:38 ` Daniel Henrique Barboza
2024-07-17 15:30 ` [RFC 2/2] target/riscv: rvv: improve performance of RISC-V vector loads and stores on large amounts of data Paolo Savini
2024-07-26 12:27 ` Daniel Henrique Barboza
2024-07-27 7:15 ` Richard Henderson
2024-09-10 11:20 ` Paolo Savini [this message]
2024-09-10 18:18 ` Richard Henderson
2024-07-26 12:31 ` [RFC 0/2] Improve the performance of unit-stride RVV ld/st on Daniel Henrique Barboza
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