* [PATCH RFC 1/3] target/arm: Implement SVE2 FCVTNT
2020-04-28 17:43 [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Stephen Long
@ 2020-04-28 17:43 ` Stephen Long
2020-04-28 17:43 ` [PATCH RFC 2/3] target/arm: Implement SVE2 FCVTLT Stephen Long
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Stephen Long @ 2020-04-28 17:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 5 +++++
target/arm/sve.decode | 4 ++++
target/arm/sve_helper.c | 20 ++++++++++++++++++++
target/arm/translate-sve.c | 16 ++++++++++++++++
4 files changed, 45 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 6b64c844bf..154593f110 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2713,3 +2713,8 @@ DEF_HELPER_FLAGS_5(sve2_sqdmlsl_idx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqdmlsl_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 22ed626784..355b8eec75 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1478,3 +1478,7 @@ STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
# SVE2 32-bit scatter non-temporal store (vector plus scalar)
STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
@rprr_scatter_store xs=0 esz=2 scale=0
+
+### SVE2 floating-point convert precision odd elements
+FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
+FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index b8c8d10c99..a35983b7cd 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7570,3 +7570,23 @@ void HELPER(fmmla_d)(void *vd, void *va, void *vn, void *vm,
d[3] = float64_add(a[3], float64_add(p0, p1, status), status);
}
}
+
+#define DO_FCVTNT(NAME, TYPEW, TYPEN, HW, HN, OP) \
+void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
+{ \
+ intptr_t i = simd_oprsz(desc); \
+ uint64_t *g = vg; \
+ do { \
+ uint64_t pg = g[(i - 1) >> 6]; \
+ do { \
+ i -= sizeof(TYPEW); \
+ if (likely((pg >> (i & 63)) & 1)) { \
+ TYPEW nn = *(TYPEW *)(vn + HW(i)); \
+ *(TYPEN *)(vd + HN(i + sizeof(TYPEN))) = OP(nn, status); \
+ } \
+ } while (i & 63); \
+ } while (i != 0); \
+}
+
+DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
+DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_4, H1_2, float64_to_float32)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 5303d2e236..d410d0024e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -8105,3 +8105,19 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
};
return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot);
}
+
+static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh);
+}
+
+static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH RFC 2/3] target/arm: Implement SVE2 FCVTLT
2020-04-28 17:43 [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Stephen Long
2020-04-28 17:43 ` [PATCH RFC 1/3] target/arm: Implement SVE2 FCVTNT Stephen Long
@ 2020-04-28 17:43 ` Stephen Long
2020-04-28 17:43 ` [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT Stephen Long
2020-06-16 19:00 ` [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Richard Henderson
3 siblings, 0 replies; 6+ messages in thread
From: Stephen Long @ 2020-04-28 17:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 5 +++++
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c | 23 +++++++++++++++++++++++
target/arm/translate-sve.c | 16 ++++++++++++++++
4 files changed, 46 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 154593f110..27a8cc2cbe 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2718,3 +2718,8 @@ DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_fcvtlt_hs, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 355b8eec75..95fc7ee32c 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1481,4 +1481,6 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
### SVE2 floating-point convert precision odd elements
FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
+FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
+FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index a35983b7cd..8461d84445 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7590,3 +7590,26 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_4, H1_2, float64_to_float32)
+
+#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
+void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
+{ \
+ intptr_t i = simd_oprsz(desc); \
+ uint64_t *g = vg; \
+ do { \
+ uint64_t pg = g[(i - 1) >> 6]; \
+ do { \
+ i -= sizeof(TYPEW); \
+ if (likely((pg >> (i & 63)) & 1)) { \
+ TYPEN nn = *(TYPEN *)(vn + HN(i + sizeof(TYPEN))); \
+ *(TYPEW *)(vd + HW(i)) = OP(nn, status); \
+ } \
+ } while (i & 63); \
+ } while (i != 0); \
+}
+
+DO_FCVTLT(sve2_fcvtlt_hs, uint32_t, uint16_t, H1_4, H1_2, sve_f16_to_f32)
+DO_FCVTLT(sve2_fcvtlt_sd, uint64_t, uint32_t, H1_4, H1_2, float32_to_float64)
+
+#undef DO_FCVTLT
+#undef DO_FCVTNT
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d410d0024e..220ff19348 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -8121,3 +8121,19 @@ static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a)
}
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds);
}
+
+static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs);
+}
+
+static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT
2020-04-28 17:43 [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Stephen Long
2020-04-28 17:43 ` [PATCH RFC 1/3] target/arm: Implement SVE2 FCVTNT Stephen Long
2020-04-28 17:43 ` [PATCH RFC 2/3] target/arm: Implement SVE2 FCVTLT Stephen Long
@ 2020-04-28 17:43 ` Stephen Long
2020-06-16 18:59 ` Richard Henderson
2020-06-16 19:00 ` [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Richard Henderson
3 siblings, 1 reply; 6+ messages in thread
From: Stephen Long @ 2020-04-28 17:43 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 2 ++
target/arm/sve.decode | 1 +
target/arm/sve_helper.c | 7 +++++++
target/arm/translate-sve.c | 8 ++++++++
4 files changed, 18 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 27a8cc2cbe..c18e4c01b0 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2714,6 +2714,8 @@ DEF_HELPER_FLAGS_5(sve2_sqdmlsl_idx_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve2_sqdmlsl_idx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_fcvtxnt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 95fc7ee32c..cb4ed70698 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1480,6 +1480,7 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
@rprr_scatter_store xs=0 esz=2 scale=0
### SVE2 floating-point convert precision odd elements
+FCVTXNT 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 8461d84445..56836d91cc 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7591,6 +7591,13 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16)
DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_4, H1_2, float64_to_float32)
+void HELPER(sve2_fcvtxnt)(void *vd, void *vn, void *vg,
+ void *status, uint32_t desc)
+{
+ set_float_rounding_mode(float_round_to_odd, status);
+ HELPER(sve2_fcvtnt_ds)(vd, vn, vg, status, desc);
+}
+
#define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \
{ \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 220ff19348..b1cf24f6e7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -8106,6 +8106,14 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot);
}
+static bool trans_FCVTXNT(DisasContext *s, arg_rpr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtxnt);
+}
+
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
{
if (!dc_isar_feature(aa64_sve2, s)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT
2020-04-28 17:43 ` [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT Stephen Long
@ 2020-06-16 18:59 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2020-06-16 18:59 UTC (permalink / raw)
To: Stephen Long, qemu-devel; +Cc: qemu-arm, apazos
On 4/28/20 10:43 AM, Stephen Long wrote:
> +void HELPER(sve2_fcvtxnt)(void *vd, void *vn, void *vg,
> + void *status, uint32_t desc)
> +{
> + set_float_rounding_mode(float_round_to_odd, status);
> + HELPER(sve2_fcvtnt_ds)(vd, vn, vg, status, desc);
> +}
This is incorrect, as it leaves the rounding mode set to odd.
I've adjusted trans_FCVTXNT to the existing do_frint_mode, which handles
switching to and back from a fixed rounding mode.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion
2020-04-28 17:43 [PATCH RFC 0/3] target/arm: Implement SVE2 fp conversion Stephen Long
` (2 preceding siblings ...)
2020-04-28 17:43 ` [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT Stephen Long
@ 2020-06-16 19:00 ` Richard Henderson
3 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2020-06-16 19:00 UTC (permalink / raw)
To: Stephen Long, qemu-devel; +Cc: qemu-arm, apazos
On 4/28/20 10:43 AM, Stephen Long wrote:
> The only insn left in this category is BFCVTNT. I couldn't find any
> helper functions for bfloats so I'm not sure how to approach this insn.
>
> Also, for insn FCVTXNT, I'm not sure if it is ok to set the status rounding
> mode to odd like that.
>
> Stephen Long (3):
> target/arm: Implement SVE2 FCVTNT
> target/arm: Implement SVE2 FCVTLT
> target/arm: Implement SVE2 FCVTXNT
Queued, with the change to the third patch as mentioned.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread