From: Richard Henderson <richard.henderson@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, add AVX
Date: Mon, 12 Sep 2022 16:33:31 +0100 [thread overview]
Message-ID: <176dac2e-16b1-6845-5341-0164b1ad0d68@linaro.org> (raw)
In-Reply-To: <20220911230418.340941-27-pbonzini@redhat.com>
On 9/12/22 00:04, Paolo Bonzini wrote:
> @@ -839,6 +910,10 @@ static bool decode_insn(DisasContext *s, CPUX86State *env, X86DecodeFunc decode_
> }
> }
> if (e->op3 != X86_TYPE_None) {
> + /*
> + * A couple instructions actually use the extra immediate byte for an Lx
> + * register operand; those are handled in the gen_* functions as one off.
> + */
> assert(e->op3 == X86_TYPE_I && e->s3 == X86_SIZE_b);
> s->rip_offset += 1;
> }
Comment should be squashed back with the code.
> +static inline void gen_binary_imm_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_epppi xmm, SSEFunc_0_epppi ymm)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
tcg_constant_i32.
> +static inline void gen_unary_imm_fp_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode,
> + SSEFunc_0_eppi xmm, SSEFunc_0_eppi ymm)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Likewise.
> +static void gen_PALIGNR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Likewise, but could simply be implemented with inline with extract2.
> +static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
tcg_constant_i32.
> +static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> +{
> + TCGv_i32 imm = tcg_const_i32(decode->immediate);
Likewise.
> static void gen_PCMPGTB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
> {
> int vec_len = sse_vec_len(s, decode);
> tcg_gen_ld8u_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_B(val)));
> + break;
> + case MO_16:
> + tcg_gen_ld16u_tl(s->T0, s->ptr1, offsetof(ZMMReg, ZMM_W(val)));
> + break;
Mailer breakage?
> + if (new_mask != 15) {
> + if ((val >> 0) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(0)));
> + if ((val >> 1) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(1)));
> + if ((val >> 2) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(2)));
> + if ((val >> 3) & 1)
> + tcg_gen_st_i32(zero, s->ptr0, offsetof(ZMMReg, ZMM_L(3)));
> + }
Missing braces.
r~
next prev parent reply other threads:[~2022-09-12 15:34 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-11 23:03 [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Paolo Bonzini
2022-09-11 23:03 ` [PATCH 01/37] target/i386: Define XMMReg and access macros, align ZMM registers Paolo Bonzini
2022-09-11 23:03 ` [PATCH 02/37] target/i386: make ldo/sto operations consistent with ldq Paolo Bonzini
2022-09-12 8:33 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 03/37] target/i386: REPZ and REPNZ are mutually exclusive Paolo Bonzini
2022-09-12 8:37 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 04/37] target/i386: introduce insn_get_addr Paolo Bonzini
2022-09-12 8:39 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 05/37] target/i386: add core of new i386 decoder Paolo Bonzini
2022-09-12 9:27 ` Richard Henderson
2022-09-12 10:54 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 06/37] target/i386: add ALU load/writeback core Paolo Bonzini
2022-09-12 10:02 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 07/37] target/i386: add CPUID[EAX=7, ECX=0].ECX to DisasContext Paolo Bonzini
2022-09-12 10:02 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 08/37] target/i386: add CPUID feature checks to new decoder Paolo Bonzini
2022-09-12 10:05 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 09/37] target/i386: add AVX_EN hflag Paolo Bonzini
2022-09-12 10:06 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 10/37] target/i386: validate VEX prefixes via the instructions' exception classes Paolo Bonzini
2022-09-12 10:39 ` Richard Henderson
2022-09-12 10:42 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 11/37] target/i386: validate SSE prefixes directly in the decoding table Paolo Bonzini
2022-09-12 10:51 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 12/37] target/i386: add scalar 0F 38 and 0F 3A instruction to new decoder Paolo Bonzini
2022-09-12 11:04 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 13/37] target/i386: remove scalar VEX instructions from old decoder Paolo Bonzini
2022-09-12 11:06 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 14/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX Paolo Bonzini
2022-09-12 11:09 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 15/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings Paolo Bonzini
2022-09-12 11:11 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 16/37] target/i386: support operand merging in binary scalar helpers Paolo Bonzini
2022-09-12 11:11 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 17/37] target/i386: provide 3-operand versions of unary " Paolo Bonzini
2022-09-12 11:14 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 18/37] target/i386: implement additional AVX comparison operators Paolo Bonzini
2022-09-12 11:19 ` Richard Henderson
2022-09-11 23:03 ` [PATCH 19/37] target/i386: Introduce 256-bit vector helpers Paolo Bonzini
2022-09-12 11:19 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Paolo Bonzini
2022-09-12 11:41 ` Richard Henderson
2022-09-13 10:56 ` Paolo Bonzini
2022-09-13 11:35 ` Richard Henderson
2022-09-12 13:01 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 21/37] target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, " Paolo Bonzini
2022-09-12 13:19 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 22/37] target/i386: reimplement 0x0f 0x50-0x5f, " Paolo Bonzini
2022-09-12 13:46 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 23/37] target/i386: reimplement 0x0f 0x78-0x7f, " Paolo Bonzini
2022-09-12 13:56 ` Richard Henderson
2022-09-14 16:17 ` Paolo Bonzini
2022-09-11 23:04 ` [PATCH 24/37] target/i386: reimplement 0x0f 0x70-0x77, " Paolo Bonzini
2022-09-12 14:29 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 25/37] target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, " Paolo Bonzini
2022-09-12 15:06 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 26/37] target/i386: reimplement 0x0f 0x3a, " Paolo Bonzini
2022-09-12 15:33 ` Richard Henderson [this message]
2022-09-11 23:04 ` [PATCH 27/37] target/i386: Use tcg gvec ops for pmovmskb Paolo Bonzini
2022-09-13 8:16 ` Richard Henderson
2022-09-14 22:59 ` Paolo Bonzini
2022-09-15 6:48 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 28/37] target/i386: reimplement 0x0f 0x38, add AVX Paolo Bonzini
2022-09-13 9:31 ` Richard Henderson
2022-09-14 17:04 ` Paolo Bonzini
2022-09-15 6:50 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 29/37] target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, " Paolo Bonzini
2022-09-13 9:44 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 30/37] target/i386: reimplement 0x0f 0x10-0x17, " Paolo Bonzini
2022-09-13 10:14 ` Richard Henderson
2022-09-14 22:45 ` Paolo Bonzini
2022-09-15 6:51 ` Richard Henderson
2022-09-13 10:38 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 31/37] target/i386: reimplement 0x0f 0x28-0x2f, " Paolo Bonzini
2022-09-13 10:24 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 32/37] target/i386: implement XSAVE and XRSTOR of AVX registers Paolo Bonzini
2022-09-13 10:27 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 33/37] target/i386: Enable AVX cpuid bits when using TCG Paolo Bonzini
2022-09-13 10:28 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 34/37] target/i386: implement VLDMXCSR/VSTMXCSR Paolo Bonzini
2022-09-13 10:32 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 35/37] tests/tcg: extend SSE tests to AVX Paolo Bonzini
2022-09-13 10:33 ` Richard Henderson
2022-09-11 23:04 ` [PATCH 36/37] target/i386: move 3DNow completely out of gen_sse Paolo Bonzini
2022-09-13 10:34 ` Richard Henderson
2022-09-13 10:39 ` [RFC PATCH 00/37] target/i386: new decoder + AVX implementation Richard Henderson
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