[PATCH qemu] hw/intc: Call sifive_plic_update() after writing interrupt enable

[~liuxu <liuxu@git.sr.ht>]

From: lxx <1733205434@qq.com>

When a guest writes to the interrupt enable register, the PLIC state
is updated but sifive_plic_update() is not called to re-evaluate the
interrupt line to the hart. This causes a lost interrupt when the
pending bit is set before the enable bit is written.

This is a level-triggered condition that must be re-evaluated whenever
any of the three factors change: pending bits, enable bits, or
threshold/priority. All other register writes that affect interrupt
delivery (priority, pending, threshold) already call
sifive_plic_update() after the write. Fix the enable register write
handler to do the same.

Signed-off-by: LIU Xu <liuxu@nucleisys.com>
---
 hw/intc/sifive_plic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9c84ff06a9f..f893384e4df 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -219,6 +219,7 @@ static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
 
         if (wordid < plic->bitfield_words) {
             plic->enable[addrid * plic->bitfield_words + wordid] = value;
+            sifive_plic_update(plic);
         } else {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "%s: Invalid enable write 0x%" HWADDR_PRIx "\n",
-- 
2.49.1