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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e1e83cab7csm7268959a91.3.2024.10.07.07.40.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Oct 2024 07:40:33 -0700 (PDT) Message-ID: <17794b7c-c337-44be-96ed-d647a28864fc@linaro.org> Date: Mon, 7 Oct 2024 07:40:31 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 00/25] misc: Use explicit endian LD/ST API To: Pierre Muller , qemu-devel@nongnu.org References: <20241004163042.85922-1-philmd@linaro.org> <5a1606e1-649f-4bda-83e9-aff8c9dfd9f4@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/7/24 00:52, Pierre Muller wrote: >> While we have never supported rx or riscv in big-endian, but there's no reason that we >> can't, and those target/ patches make things harder. Since target/ will *always* have >> TARGET_BIG_ENDIAN available, I don't see that we're saving anything there. > >   Isn't this also true for the sparc CPU? Yes, I'd forgotten about that. Indeed, Sparc v9 has a couple of PSTATE bits that set the endianness, exactly like Arm and Power, which qemu has not implemented for system mode. r~