* [PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-09-01 6:50 ` Philippe Mathieu-Daudé
2025-07-30 3:01 ` [PATCH v4 02/19] target/loongarch: Define function loongarch_cpu_post_init as static Bibo Mao
` (17 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
Move function definition specified with kvm to the corresponding
directory. Also remove header file "cpu.h" including outside of
macro QEMU_KVM_LOONGARCH_H.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/loongarch/virt.c | 1 +
target/loongarch/cpu.h | 9 ---------
target/loongarch/kvm/kvm_loongarch.h | 4 ++--
3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index b15ada2078..31215b7785 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -46,6 +46,7 @@
#include "hw/block/flash.h"
#include "hw/virtio/virtio-iommu.h"
#include "qemu/error-report.h"
+#include "kvm/kvm_loongarch.h"
static void virt_get_veiointc(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 9538e8d61d..bbe6db33f1 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -496,13 +496,4 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
void loongarch_cpu_post_init(Object *obj);
-#ifdef CONFIG_KVM
-void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu);
-#else
-static inline void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu)
-{
-}
-#endif
-void kvm_loongarch_init_irq_routing(void);
-
#endif /* LOONGARCH_CPU_H */
diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kvm_loongarch.h
index 1051a341ec..51475675d6 100644
--- a/target/loongarch/kvm/kvm_loongarch.h
+++ b/target/loongarch/kvm/kvm_loongarch.h
@@ -5,11 +5,11 @@
* Copyright (c) 2023 Loongson Technology Corporation Limited
*/
-#include "cpu.h"
-
#ifndef QEMU_KVM_LOONGARCH_H
#define QEMU_KVM_LOONGARCH_H
+void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu);
+void kvm_loongarch_init_irq_routing(void);
int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
void kvm_arch_reset_vcpu(CPUState *cs);
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory
2025-07-30 3:01 ` [PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory Bibo Mao
@ 2025-09-01 6:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 36+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-09-01 6:50 UTC (permalink / raw)
To: Bibo Mao, Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
On 30/7/25 05:01, Bibo Mao wrote:
> Move function definition specified with kvm to the corresponding
> directory. Also remove header file "cpu.h" including outside of
> macro QEMU_KVM_LOONGARCH_H.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> hw/loongarch/virt.c | 1 +
> target/loongarch/cpu.h | 9 ---------
> target/loongarch/kvm/kvm_loongarch.h | 4 ++--
> 3 files changed, 3 insertions(+), 11 deletions(-)
> diff --git a/target/loongarch/kvm/kvm_loongarch.h b/target/loongarch/kvm/kvm_loongarch.h
> index 1051a341ec..51475675d6 100644
> --- a/target/loongarch/kvm/kvm_loongarch.h
> +++ b/target/loongarch/kvm/kvm_loongarch.h
> @@ -5,11 +5,11 @@
> * Copyright (c) 2023 Loongson Technology Corporation Limited
> */
>
> -#include "cpu.h"
> -
Technically we need "target/loongarch/cpu-qom.h" to get
LoongArchCPU's declaration.
> #ifndef QEMU_KVM_LOONGARCH_H
> #define QEMU_KVM_LOONGARCH_H
>
> +void kvm_loongarch_cpu_post_init(LoongArchCPU *cpu);
> +void kvm_loongarch_init_irq_routing(void);
> int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level);
> void kvm_arch_reset_vcpu(CPUState *cs);
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 02/19] target/loongarch: Define function loongarch_cpu_post_init as static
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
2025-07-30 3:01 ` [PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 3:01 ` [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB Bibo Mao
` (16 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
Function loongarch_cpu_post_init() is implemented and used in the
same file target/loongarch/cpu.c, it can be defined as static function.
This patch moves implementation about function loongarch_cpu_post_init()
before it is referenced. And it is only code movement, no function
change.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu.c | 180 ++++++++++++++++++++---------------------
target/loongarch/cpu.h | 2 -
2 files changed, 90 insertions(+), 92 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index abad84c054..b96429ffb1 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -422,6 +422,96 @@ static void loongarch_la464_init_csr(Object *obj)
#endif
}
+static bool loongarch_get_lsx(Object *obj, Error **errp)
+{
+ return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
+}
+
+static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ uint32_t val;
+
+ cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+ if (cpu->lsx == ON_OFF_AUTO_OFF) {
+ cpu->lasx = ON_OFF_AUTO_OFF;
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
+ error_setg(errp, "Failed to disable LSX since LASX is enabled");
+ return;
+ }
+ }
+
+ if (kvm_enabled()) {
+ /* kvm feature detection in function kvm_arch_init_vcpu */
+ return;
+ }
+
+ /* LSX feature detection in TCG mode */
+ val = cpu->env.cpucfg[2];
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
+ if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
+ error_setg(errp, "Failed to enable LSX in TCG mode");
+ return;
+ }
+ } else {
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
+ val = cpu->env.cpucfg[2];
+ }
+
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
+}
+
+static bool loongarch_get_lasx(Object *obj, Error **errp)
+{
+ return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
+}
+
+static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ uint32_t val;
+
+ cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+ if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
+ error_setg(errp, "Failed to enable LASX since lSX is disabled");
+ return;
+ }
+
+ if (kvm_enabled()) {
+ /* kvm feature detection in function kvm_arch_init_vcpu */
+ return;
+ }
+
+ /* LASX feature detection in TCG mode */
+ val = cpu->env.cpucfg[2];
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
+ if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
+ error_setg(errp, "Failed to enable LASX in TCG mode");
+ return;
+ }
+ }
+
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
+}
+
+static void loongarch_cpu_post_init(Object *obj)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+
+ cpu->lbt = ON_OFF_AUTO_OFF;
+ cpu->pmu = ON_OFF_AUTO_OFF;
+ cpu->lsx = ON_OFF_AUTO_AUTO;
+ cpu->lasx = ON_OFF_AUTO_AUTO;
+ object_property_add_bool(obj, "lsx", loongarch_get_lsx,
+ loongarch_set_lsx);
+ object_property_add_bool(obj, "lasx", loongarch_get_lasx,
+ loongarch_set_lasx);
+ /* lbt is enabled only in kvm mode, not supported in tcg mode */
+ if (kvm_enabled()) {
+ kvm_loongarch_cpu_post_init(cpu);
+ }
+}
+
static void loongarch_la464_initfn(Object *obj)
{
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
@@ -683,96 +773,6 @@ static void loongarch_cpu_unrealizefn(DeviceState *dev)
lacc->parent_unrealize(dev);
}
-static bool loongarch_get_lsx(Object *obj, Error **errp)
-{
- return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
-}
-
-static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
-{
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
- uint32_t val;
-
- cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
- if (cpu->lsx == ON_OFF_AUTO_OFF) {
- cpu->lasx = ON_OFF_AUTO_OFF;
- if (cpu->lasx == ON_OFF_AUTO_ON) {
- error_setg(errp, "Failed to disable LSX since LASX is enabled");
- return;
- }
- }
-
- if (kvm_enabled()) {
- /* kvm feature detection in function kvm_arch_init_vcpu */
- return;
- }
-
- /* LSX feature detection in TCG mode */
- val = cpu->env.cpucfg[2];
- if (cpu->lsx == ON_OFF_AUTO_ON) {
- if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
- error_setg(errp, "Failed to enable LSX in TCG mode");
- return;
- }
- } else {
- cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
- val = cpu->env.cpucfg[2];
- }
-
- cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
-}
-
-static bool loongarch_get_lasx(Object *obj, Error **errp)
-{
- return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
-}
-
-static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
-{
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
- uint32_t val;
-
- cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
- if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
- error_setg(errp, "Failed to enable LASX since lSX is disabled");
- return;
- }
-
- if (kvm_enabled()) {
- /* kvm feature detection in function kvm_arch_init_vcpu */
- return;
- }
-
- /* LASX feature detection in TCG mode */
- val = cpu->env.cpucfg[2];
- if (cpu->lasx == ON_OFF_AUTO_ON) {
- if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
- error_setg(errp, "Failed to enable LASX in TCG mode");
- return;
- }
- }
-
- cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
-}
-
-void loongarch_cpu_post_init(Object *obj)
-{
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-
- cpu->lbt = ON_OFF_AUTO_OFF;
- cpu->pmu = ON_OFF_AUTO_OFF;
- cpu->lsx = ON_OFF_AUTO_AUTO;
- cpu->lasx = ON_OFF_AUTO_AUTO;
- object_property_add_bool(obj, "lsx", loongarch_get_lsx,
- loongarch_set_lsx);
- object_property_add_bool(obj, "lasx", loongarch_get_lasx,
- loongarch_set_lasx);
- /* lbt is enabled only in kvm mode, not supported in tcg mode */
- if (kvm_enabled()) {
- kvm_loongarch_cpu_post_init(cpu);
- }
-}
-
static void loongarch_cpu_init(Object *obj)
{
#ifndef CONFIG_USER_ONLY
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index bbe6db33f1..7731f6acdc 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -494,6 +494,4 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
#define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU
-void loongarch_cpu_post_init(Object *obj);
-
#endif /* LOONGARCH_CPU_H */
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
2025-07-30 3:01 ` [PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory Bibo Mao
2025-07-30 3:01 ` [PATCH v4 02/19] target/loongarch: Define function loongarch_cpu_post_init as static Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-08-28 2:38 ` Bibo Mao
2025-08-29 1:27 ` gaosong
2025-07-30 3:01 ` [PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h Bibo Mao
` (15 subsequent siblings)
18 siblings, 2 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With VTLB different TLB entry may have different page size, and
page size is set in PS field of TLB entry. However with STLB, all
the TLB entries have the same page size, page size comes from register
CSR_STLBPS, PS field of TLB entry is not used.
Here PS field of TLB entry is used with all TLB entries, even with
STLB. It is convenient with TLB maintainance operation.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 41 ++++++++-----------------------
1 file changed, 10 insertions(+), 31 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 8872593ff0..3ea0e153b1 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -110,11 +110,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
if (!tlb_e) {
return;
}
- if (index >= LOONGARCH_STLB) {
- tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
- } else {
- tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
- }
+
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
@@ -173,11 +170,8 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
lo1 = env->CSR_TLBELO1;
}
- /* Only MTLB has the ps fields */
- if (index >= LOONGARCH_STLB) {
- tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
- }
-
+ /* Store page size in field PS */
+ tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
@@ -283,12 +277,7 @@ void helper_tlbrd(CPULoongArchState *env)
index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
tlb = &env->tlb[index];
-
- if (index >= LOONGARCH_STLB) {
- tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
- } else {
- tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
- }
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
if (!tlb_e) {
@@ -476,11 +465,8 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
if (!tlb_e) {
continue;
}
- if (i >= LOONGARCH_STLB) {
- tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
- } else {
- tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
- }
+
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
@@ -509,11 +495,8 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
if (!tlb_e) {
continue;
}
- if (i >= LOONGARCH_STLB) {
- tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
- } else {
- tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
- }
+
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
@@ -673,11 +656,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
uint64_t tlb_entry, tlb_ppn;
uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
- if (index >= LOONGARCH_STLB) {
- tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
- } else {
- tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
- }
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
n = (address >> tlb_ps) & 0x1;/* Odd or even */
tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB
2025-07-30 3:01 ` [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB Bibo Mao
@ 2025-08-28 2:38 ` Bibo Mao
2025-08-29 1:27 ` gaosong
1 sibling, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-08-28 2:38 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
ping for this patch only so that acked patch can be merge at first.
For patch 14, 16-19, I can give up the method to flush QEMU TLB with
MMU_USER_IDX mmu idx only, it can be done in late.
Regards
Bibo Mao
On 2025/7/30 上午11:01, Bibo Mao wrote:
> With VTLB different TLB entry may have different page size, and
> page size is set in PS field of TLB entry. However with STLB, all
> the TLB entries have the same page size, page size comes from register
> CSR_STLBPS, PS field of TLB entry is not used.
>
> Here PS field of TLB entry is used with all TLB entries, even with
> STLB. It is convenient with TLB maintainance operation.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/tcg/tlb_helper.c | 41 ++++++++-----------------------
> 1 file changed, 10 insertions(+), 31 deletions(-)
>
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 8872593ff0..3ea0e153b1 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -110,11 +110,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
> if (!tlb_e) {
> return;
> }
> - if (index >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> +
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
> mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
>
> @@ -173,11 +170,8 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
> lo1 = env->CSR_TLBELO1;
> }
>
> - /* Only MTLB has the ps fields */
> - if (index >= LOONGARCH_STLB) {
> - tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
> - }
> -
> + /* Store page size in field PS */
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
> tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
> tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
> csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> @@ -283,12 +277,7 @@ void helper_tlbrd(CPULoongArchState *env)
>
> index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> tlb = &env->tlb[index];
> -
> - if (index >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
>
> if (!tlb_e) {
> @@ -476,11 +465,8 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
> if (!tlb_e) {
> continue;
> }
> - if (i >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> +
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
> compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> @@ -509,11 +495,8 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
> if (!tlb_e) {
> continue;
> }
> - if (i >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> +
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
> compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> @@ -673,11 +656,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
> uint64_t tlb_entry, tlb_ppn;
> uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
>
> - if (index >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> n = (address >> tlb_ps) & 0x1;/* Odd or even */
>
> tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
>
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB
2025-07-30 3:01 ` [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB Bibo Mao
2025-08-28 2:38 ` Bibo Mao
@ 2025-08-29 1:27 ` gaosong
1 sibling, 0 replies; 36+ messages in thread
From: gaosong @ 2025-08-29 1:27 UTC (permalink / raw)
To: Bibo Mao; +Cc: Richard Henderson, Jiaxun Yang, qemu-devel
在 2025/7/30 上午11:01, Bibo Mao 写道:
> With VTLB different TLB entry may have different page size, and
> page size is set in PS field of TLB entry. However with STLB, all
> the TLB entries have the same page size, page size comes from register
> CSR_STLBPS, PS field of TLB entry is not used.
>
> Here PS field of TLB entry is used with all TLB entries, even with
> STLB. It is convenient with TLB maintainance operation.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/tcg/tlb_helper.c | 41 ++++++++-----------------------
> 1 file changed, 10 insertions(+), 31 deletions(-)
Reviewed-by: Song Gao <gaosong@loongson.cn>
Tested-by: Song Gao <gaosong@loongson.cn>
Thanks.
Song Gao
> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 8872593ff0..3ea0e153b1 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -110,11 +110,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
> if (!tlb_e) {
> return;
> }
> - if (index >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> +
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
> mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
>
> @@ -173,11 +170,8 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
> lo1 = env->CSR_TLBELO1;
> }
>
> - /* Only MTLB has the ps fields */
> - if (index >= LOONGARCH_STLB) {
> - tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
> - }
> -
> + /* Store page size in field PS */
> + tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
> tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
> tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
> csr_asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
> @@ -283,12 +277,7 @@ void helper_tlbrd(CPULoongArchState *env)
>
> index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
> tlb = &env->tlb[index];
> -
> - if (index >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
>
> if (!tlb_e) {
> @@ -476,11 +465,8 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
> if (!tlb_e) {
> continue;
> }
> - if (i >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> +
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
> compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> @@ -509,11 +495,8 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
> if (!tlb_e) {
> continue;
> }
> - if (i >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> +
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
> vpn = (addr & TARGET_VIRT_MASK) >> (tlb_ps + 1);
> compare_shift = tlb_ps + 1 - R_TLB_MISC_VPPN_SHIFT;
> @@ -673,11 +656,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
> uint64_t tlb_entry, tlb_ppn;
> uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
>
> - if (index >= LOONGARCH_STLB) {
> - tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> - } else {
> - tlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
> - }
> + tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
> n = (address >> tlb_ps) & 0x1;/* Odd or even */
>
> tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (2 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-09-01 6:47 ` Philippe Mathieu-Daudé
2025-07-30 3:01 ` [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition Bibo Mao
` (14 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
New header file cpu-mmu.h is added and move mmu relative function
declaration to this file.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu-mmu.h | 30 ++++++++++++++++++++++++++++++
target/loongarch/cpu.c | 1 +
target/loongarch/cpu_helper.c | 1 +
target/loongarch/internals.h | 20 --------------------
target/loongarch/tcg/csr_helper.c | 1 +
target/loongarch/tcg/tlb_helper.c | 1 +
6 files changed, 34 insertions(+), 20 deletions(-)
create mode 100644 target/loongarch/cpu-mmu.h
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
new file mode 100644
index 0000000000..4c5cbd7425
--- /dev/null
+++ b/target/loongarch/cpu-mmu.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch CPU parameters for QEMU.
+ *
+ * Copyright (c) 2025 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_CPU_MMU_H
+#define LOONGARCH_CPU_MMU_H
+
+enum {
+ TLBRET_MATCH = 0,
+ TLBRET_BADADDR = 1,
+ TLBRET_NOMATCH = 2,
+ TLBRET_INVALID = 3,
+ TLBRET_DIRTY = 4,
+ TLBRET_RI = 5,
+ TLBRET_XI = 6,
+ TLBRET_PE = 7,
+};
+
+bool check_ps(CPULoongArchState *ent, uint8_t ps);
+int get_physical_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx, int is_debug);
+void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+ uint64_t *dir_width, target_ulong level);
+hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+
+#endif /* LOONGARCH_CPU_MMU_H */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index b96429ffb1..990985708e 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -17,6 +17,7 @@
#include "hw/qdev-properties.h"
#include "exec/translation-block.h"
#include "cpu.h"
+#include "cpu-mmu.h"
#include "internals.h"
#include "fpu/softfloat-helpers.h"
#include "csr.h"
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index e172b11ce1..2e8d3d7cfb 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -13,6 +13,7 @@
#include "exec/target_page.h"
#include "internals.h"
#include "cpu-csr.h"
+#include "cpu-mmu.h"
#include "tcg/tcg_loongarch.h"
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index a7384b0d31..e50d109767 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -32,19 +32,6 @@ void restore_fp_status(CPULoongArchState *env);
#endif
#ifndef CONFIG_USER_ONLY
-enum {
- TLBRET_MATCH = 0,
- TLBRET_BADADDR = 1,
- TLBRET_NOMATCH = 2,
- TLBRET_INVALID = 3,
- TLBRET_DIRTY = 4,
- TLBRET_RI = 5,
- TLBRET_XI = 6,
- TLBRET_PE = 7,
-};
-
-bool check_ps(CPULoongArchState *ent, uint8_t ps);
-
extern const VMStateDescription vmstate_loongarch_cpu;
void loongarch_cpu_set_irq(void *opaque, int irq, int level);
@@ -54,13 +41,6 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
uint64_t value);
-int get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- MMUAccessType access_type, int mmu_idx, int is_debug);
-void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
- uint64_t *dir_width, target_ulong level);
-hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-
#endif /* !CONFIG_USER_ONLY */
uint64_t read_fcc(CPULoongArchState *env);
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 28b1bb86bd..0d99e2c92b 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -16,6 +16,7 @@
#include "accel/tcg/cpu-ldst.h"
#include "hw/irq.h"
#include "cpu-csr.h"
+#include "cpu-mmu.h"
target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
{
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 3ea0e153b1..1f49619e7f 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -10,6 +10,7 @@
#include "qemu/guest-random.h"
#include "cpu.h"
+#include "cpu-mmu.h"
#include "internals.h"
#include "exec/helper-proto.h"
#include "exec/cputlb.h"
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h
2025-07-30 3:01 ` [PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h Bibo Mao
@ 2025-09-01 6:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 36+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-09-01 6:47 UTC (permalink / raw)
To: Bibo Mao, Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
On 30/7/25 05:01, Bibo Mao wrote:
> New header file cpu-mmu.h is added and move mmu relative function
> declaration to this file.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/loongarch/cpu-mmu.h | 30 ++++++++++++++++++++++++++++++
> target/loongarch/cpu.c | 1 +
> target/loongarch/cpu_helper.c | 1 +
> target/loongarch/internals.h | 20 --------------------
> target/loongarch/tcg/csr_helper.c | 1 +
> target/loongarch/tcg/tlb_helper.c | 1 +
> 6 files changed, 34 insertions(+), 20 deletions(-)
> create mode 100644 target/loongarch/cpu-mmu.h
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (3 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 5:53 ` Richard Henderson
2025-09-01 6:47 ` Philippe Mathieu-Daudé
2025-07-30 3:01 ` [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address() Bibo Mao
` (13 subsequent siblings)
18 siblings, 2 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
There is mixed usage between enum variable TLBRET_xxx and int type,
here add enum type TLBRet definition and replace int type variable
with enum type TLBRet in some functions.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu-mmu.h | 27 ++++++++++++++-------------
target/loongarch/cpu_helper.c | 26 ++++++++++++++------------
target/loongarch/tcg/tcg_loongarch.h | 7 ++++---
target/loongarch/tcg/tlb_helper.c | 16 ++++++++--------
4 files changed, 40 insertions(+), 36 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index 4c5cbd7425..cbe6f37773 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -8,21 +8,22 @@
#ifndef LOONGARCH_CPU_MMU_H
#define LOONGARCH_CPU_MMU_H
-enum {
- TLBRET_MATCH = 0,
- TLBRET_BADADDR = 1,
- TLBRET_NOMATCH = 2,
- TLBRET_INVALID = 3,
- TLBRET_DIRTY = 4,
- TLBRET_RI = 5,
- TLBRET_XI = 6,
- TLBRET_PE = 7,
-};
+typedef enum TLBRet {
+ TLBRET_MATCH,
+ TLBRET_BADADDR,
+ TLBRET_NOMATCH,
+ TLBRET_INVALID,
+ TLBRET_DIRTY,
+ TLBRET_RI,
+ TLBRET_XI,
+ TLBRET_PE,
+} TLBRet;
bool check_ps(CPULoongArchState *ent, uint8_t ps);
-int get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- MMUAccessType access_type, int mmu_idx, int is_debug);
+TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx,
+ int is_debug);
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, target_ulong level);
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 2e8d3d7cfb..cc7cff674e 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -44,8 +44,9 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
}
}
-static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address)
+static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
+ hwaddr *physical,
+ int *prot, target_ulong address)
{
CPUState *cs = env_cpu(env);
target_ulong index, phys;
@@ -116,15 +117,15 @@ static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *physical,
/* mask other attribute bits */
*physical = base & TARGET_PAGE_MASK;
- return 0;
+ return TLBRET_MATCH;
}
-static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- MMUAccessType access_type, int mmu_idx,
- int is_debug)
+static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx,
+ int is_debug)
{
- int ret;
+ TLBRet ret;
if (tcg_enabled()) {
ret = loongarch_get_addr_from_tlb(env, physical, prot, address,
@@ -158,9 +159,10 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
}
}
-int get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- MMUAccessType access_type, int mmu_idx, int is_debug)
+TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx,
+ int is_debug)
{
int user_mode = mmu_idx == MMU_USER_IDX;
int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
@@ -214,7 +216,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
- cpu_mmu_index(cs, false), 1) != 0) {
+ cpu_mmu_index(cs, false), 1) != TLBRET_MATCH) {
return -1;
}
return phys_addr;
diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
index fd4e116022..488700c3c3 100644
--- a/target/loongarch/tcg/tcg_loongarch.h
+++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -7,6 +7,7 @@
#ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H
#define TARGET_LOONGARCH_TCG_LOONGARCH_H
#include "cpu.h"
+#include "cpu-mmu.h"
void loongarch_csr_translate_init(void);
@@ -14,8 +15,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-int loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- MMUAccessType access_type, int mmu_idx);
+TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx);
#endif /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 1f49619e7f..4a2a565985 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -30,7 +30,7 @@ bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
}
static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
- MMUAccessType access_type, int tlb_error)
+ MMUAccessType access_type, TLBRet tlb_error)
{
CPUState *cs = env_cpu(env);
@@ -517,7 +517,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPULoongArchState *env = cpu_env(cs);
hwaddr physical;
int prot;
- int ret;
+ TLBRet ret;
/* Data access */
ret = get_physical_address(env, &physical, &prot, address,
@@ -648,9 +648,9 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
}
-static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- int access_type, int index, int mmu_idx)
+static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ int access_type, int index, int mmu_idx)
{
LoongArchTLB *tlb = &env->tlb[index];
uint64_t plv = mmu_idx;
@@ -713,9 +713,9 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
return TLBRET_MATCH;
}
-int loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- MMUAccessType access_type, int mmu_idx)
+TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
+ int *prot, target_ulong address,
+ MMUAccessType access_type, int mmu_idx)
{
int index, match;
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition
2025-07-30 3:01 ` [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition Bibo Mao
@ 2025-07-30 5:53 ` Richard Henderson
2025-09-01 6:47 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2025-07-30 5:53 UTC (permalink / raw)
To: Bibo Mao, Song Gao; +Cc: Jiaxun Yang, qemu-devel
On 7/29/25 17:01, Bibo Mao wrote:
> There is mixed usage between enum variable TLBRET_xxx and int type,
> here add enum type TLBRet definition and replace int type variable
> with enum type TLBRet in some functions.
>
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
> target/loongarch/cpu-mmu.h | 27 ++++++++++++++-------------
> target/loongarch/cpu_helper.c | 26 ++++++++++++++------------
> target/loongarch/tcg/tcg_loongarch.h | 7 ++++---
> target/loongarch/tcg/tlb_helper.c | 16 ++++++++--------
> 4 files changed, 40 insertions(+), 36 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition
2025-07-30 3:01 ` [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition Bibo Mao
2025-07-30 5:53 ` Richard Henderson
@ 2025-09-01 6:47 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 36+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-09-01 6:47 UTC (permalink / raw)
To: Bibo Mao, Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
On 30/7/25 05:01, Bibo Mao wrote:
> There is mixed usage between enum variable TLBRET_xxx and int type,
> here add enum type TLBRet definition and replace int type variable
> with enum type TLBRet in some functions.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/cpu-mmu.h | 27 ++++++++++++++-------------
> target/loongarch/cpu_helper.c | 26 ++++++++++++++------------
> target/loongarch/tcg/tcg_loongarch.h | 7 ++++---
> target/loongarch/tcg/tlb_helper.c | 16 ++++++++--------
> 4 files changed, 40 insertions(+), 36 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address()
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (4 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 5:54 ` Richard Henderson
2025-09-01 6:46 ` Philippe Mathieu-Daudé
2025-07-30 3:01 ` [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry() Bibo Mao
` (12 subsequent siblings)
18 siblings, 2 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
Replace target_ulong type with vaddr in function get_physical_address()
and the same with its calling functions.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu-mmu.h | 2 +-
target/loongarch/cpu_helper.c | 9 ++++-----
target/loongarch/tcg/tlb_helper.c | 11 ++++++-----
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index cbe6f37773..dffc12820f 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -21,7 +21,7 @@ typedef enum TLBRet {
bool check_ps(CPULoongArchState *ent, uint8_t ps);
TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx,
int is_debug);
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index cc7cff674e..547b9a0877 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -46,7 +46,7 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
hwaddr *physical,
- int *prot, target_ulong address)
+ int *prot, vaddr address)
{
CPUState *cs = env_cpu(env);
target_ulong index, phys;
@@ -121,7 +121,7 @@ static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
}
static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx,
int is_debug)
{
@@ -147,8 +147,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
return TLBRET_NOMATCH;
}
-static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
- target_ulong dmw)
+static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, target_ulong dmw)
{
if (is_la64(env)) {
return va & TARGET_VIRT_MASK;
@@ -160,7 +159,7 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
}
TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx,
int is_debug)
{
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 4a2a565985..3d09f18020 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -29,7 +29,7 @@ bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
return BIT_ULL(tlb_ps) & (env->CSR_PRCFG2);
}
-static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
+static void raise_mmu_exception(CPULoongArchState *env, vaddr address,
MMUAccessType access_type, TLBRet tlb_error)
{
CPUState *cs = env_cpu(env);
@@ -198,7 +198,7 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
* field in tlb entry contains bit[47:13], so need adjust.
* virt_vpn = vaddr[47:13]
*/
-static bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
+static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
int *index)
{
LoongArchTLB *tlb;
@@ -649,8 +649,9 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
}
static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
- int access_type, int index, int mmu_idx)
+ int *prot, vaddr address,
+ int access_type, int index,
+ int mmu_idx)
{
LoongArchTLB *tlb = &env->tlb[index];
uint64_t plv = mmu_idx;
@@ -714,7 +715,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
}
TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx)
{
int index, match;
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address()
2025-07-30 3:01 ` [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address() Bibo Mao
@ 2025-07-30 5:54 ` Richard Henderson
2025-09-01 6:46 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2025-07-30 5:54 UTC (permalink / raw)
To: Bibo Mao, Song Gao; +Cc: Jiaxun Yang, qemu-devel
On 7/29/25 17:01, Bibo Mao wrote:
> Replace target_ulong type with vaddr in function get_physical_address()
> and the same with its calling functions.
>
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
> target/loongarch/cpu-mmu.h | 2 +-
> target/loongarch/cpu_helper.c | 9 ++++-----
> target/loongarch/tcg/tlb_helper.c | 11 ++++++-----
> 3 files changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address()
2025-07-30 3:01 ` [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address() Bibo Mao
2025-07-30 5:54 ` Richard Henderson
@ 2025-09-01 6:46 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 36+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-09-01 6:46 UTC (permalink / raw)
To: Bibo Mao, Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
On 30/7/25 05:01, Bibo Mao wrote:
> Replace target_ulong type with vaddr in function get_physical_address()
> and the same with its calling functions.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/cpu-mmu.h | 2 +-
> target/loongarch/cpu_helper.c | 9 ++++-----
> target/loongarch/tcg/tlb_helper.c | 11 ++++++-----
> 3 files changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry()
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (5 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address() Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 5:54 ` Richard Henderson
2025-09-01 6:50 ` Philippe Mathieu-Daudé
2025-07-30 3:01 ` [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte() Bibo Mao
` (11 subsequent siblings)
18 siblings, 2 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
Enum type MMUAccessType is used in function loongarch_map_tlb_entry()
rather than int type, and keep consistent with its caller function.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 3d09f18020..915b1aadb5 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -650,7 +650,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
int *prot, vaddr address,
- int access_type, int index,
+ MMUAccessType access_type, int index,
int mmu_idx)
{
LoongArchTLB *tlb = &env->tlb[index];
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry()
2025-07-30 3:01 ` [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry() Bibo Mao
@ 2025-07-30 5:54 ` Richard Henderson
2025-09-01 6:50 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2025-07-30 5:54 UTC (permalink / raw)
To: Bibo Mao, Song Gao; +Cc: Jiaxun Yang, qemu-devel
On 7/29/25 17:01, Bibo Mao wrote:
> Enum type MMUAccessType is used in function loongarch_map_tlb_entry()
> rather than int type, and keep consistent with its caller function.
>
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
> target/loongarch/tcg/tlb_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry()
2025-07-30 3:01 ` [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry() Bibo Mao
2025-07-30 5:54 ` Richard Henderson
@ 2025-09-01 6:50 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 36+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-09-01 6:50 UTC (permalink / raw)
To: Bibo Mao, Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
On 30/7/25 05:01, Bibo Mao wrote:
> Enum type MMUAccessType is used in function loongarch_map_tlb_entry()
> rather than int type, and keep consistent with its caller function.
>
> Signed-off-by: Bibo Mao <maobibo@loongson.cn>
> ---
> target/loongarch/tcg/tlb_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte()
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (6 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry() Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 5:55 ` Richard Henderson
2025-07-30 3:01 ` [PATCH v4 09/19] target/loongarch: Use loongarch_check_pte in loongarch_page_table_walker Bibo Mao
` (10 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
Common function loongarch_check_pte() is to check tlb entry, return
the physical address and access priviledge if found. Also it can be
used with page table entry, which is used in page table walker.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu-mmu.h | 10 +++++
target/loongarch/cpu_helper.c | 61 ++++++++++++++++++++++++++++
target/loongarch/tcg/tlb_helper.c | 66 ++++++-------------------------
3 files changed, 83 insertions(+), 54 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index dffc12820f..be3d11d3c1 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -19,7 +19,17 @@ typedef enum TLBRet {
TLBRET_PE,
} TLBRet;
+typedef struct MMUContext {
+ vaddr addr;
+ uint64_t pte;
+ hwaddr physical;
+ int ps; /* page size shift */
+ int prot;
+} MMUContext;
+
bool check_ps(CPULoongArchState *ent, uint8_t ps);
+TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
+ MMUAccessType access_type, int mmu_idx);
TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, vaddr address,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 547b9a0877..5b140316bc 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -44,6 +44,67 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
}
}
+TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
+ MMUAccessType access_type, int mmu_idx)
+{
+ uint64_t plv = mmu_idx;
+ uint64_t tlb_entry, tlb_ppn;
+ uint8_t tlb_ps, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
+
+ tlb_entry = context->pte;
+ tlb_ps = context->ps;
+ tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
+ tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
+ tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
+ if (is_la64(env)) {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+ tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+ tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+ tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+ } else {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+ tlb_nx = 0;
+ tlb_nr = 0;
+ tlb_rplv = 0;
+ }
+
+ /* Remove sw bit between bit12 -- bit PS*/
+ tlb_ppn = tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1));
+
+ /* Check access rights */
+ if (!tlb_v) {
+ return TLBRET_INVALID;
+ }
+
+ if (access_type == MMU_INST_FETCH && tlb_nx) {
+ return TLBRET_XI;
+ }
+
+ if (access_type == MMU_DATA_LOAD && tlb_nr) {
+ return TLBRET_RI;
+ }
+
+ if (((tlb_rplv == 0) && (plv > tlb_plv)) ||
+ ((tlb_rplv == 1) && (plv != tlb_plv))) {
+ return TLBRET_PE;
+ }
+
+ if ((access_type == MMU_DATA_STORE) && !tlb_d) {
+ return TLBRET_DIRTY;
+ }
+
+ context->physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
+ (context->addr & MAKE_64BIT_MASK(0, tlb_ps));
+ context->prot = PAGE_READ;
+ if (tlb_d) {
+ context->prot |= PAGE_WRITE;
+ }
+ if (!tlb_nx) {
+ context->prot |= PAGE_EXEC;
+ }
+ return TLBRET_MATCH;
+}
+
static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
hwaddr *physical,
int *prot, vaddr address)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 915b1aadb5..10322da62e 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -654,64 +654,22 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
int mmu_idx)
{
LoongArchTLB *tlb = &env->tlb[index];
- uint64_t plv = mmu_idx;
- uint64_t tlb_entry, tlb_ppn;
- uint8_t tlb_ps, n, tlb_v, tlb_d, tlb_plv, tlb_nx, tlb_nr, tlb_rplv;
+ uint8_t tlb_ps, n;
+ MMUContext context;
+ TLBRet ret;
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
n = (address >> tlb_ps) & 0x1;/* Odd or even */
+ context.pte = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
+ context.addr = address;
+ context.ps = tlb_ps;
+ ret = loongarch_check_pte(env, &context, access_type, mmu_idx);
+ if (ret == TLBRET_MATCH) {
+ *physical = context.physical;
+ *prot = context.prot;
+ }
- tlb_entry = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
- tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
- tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
- tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
- if (is_la64(env)) {
- tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
- tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
- tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
- tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
- } else {
- tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
- tlb_nx = 0;
- tlb_nr = 0;
- tlb_rplv = 0;
- }
-
- /* Remove sw bit between bit12 -- bit PS*/
- tlb_ppn = tlb_ppn & ~(((0x1UL << (tlb_ps - 12)) - 1));
-
- /* Check access rights */
- if (!tlb_v) {
- return TLBRET_INVALID;
- }
-
- if (access_type == MMU_INST_FETCH && tlb_nx) {
- return TLBRET_XI;
- }
-
- if (access_type == MMU_DATA_LOAD && tlb_nr) {
- return TLBRET_RI;
- }
-
- if (((tlb_rplv == 0) && (plv > tlb_plv)) ||
- ((tlb_rplv == 1) && (plv != tlb_plv))) {
- return TLBRET_PE;
- }
-
- if ((access_type == MMU_DATA_STORE) && !tlb_d) {
- return TLBRET_DIRTY;
- }
-
- *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
- (address & MAKE_64BIT_MASK(0, tlb_ps));
- *prot = PAGE_READ;
- if (tlb_d) {
- *prot |= PAGE_WRITE;
- }
- if (!tlb_nx) {
- *prot |= PAGE_EXEC;
- }
- return TLBRET_MATCH;
+ return ret;
}
TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte()
2025-07-30 3:01 ` [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte() Bibo Mao
@ 2025-07-30 5:55 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2025-07-30 5:55 UTC (permalink / raw)
To: Bibo Mao, Song Gao; +Cc: Jiaxun Yang, qemu-devel
On 7/29/25 17:01, Bibo Mao wrote:
> Common function loongarch_check_pte() is to check tlb entry, return
> the physical address and access priviledge if found. Also it can be
> used with page table entry, which is used in page table walker.
>
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
> target/loongarch/cpu-mmu.h | 10 +++++
> target/loongarch/cpu_helper.c | 61 ++++++++++++++++++++++++++++
> target/loongarch/tcg/tlb_helper.c | 66 ++++++-------------------------
> 3 files changed, 83 insertions(+), 54 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 09/19] target/loongarch: Use loongarch_check_pte in loongarch_page_table_walker
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (7 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte() Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 3:01 ` [PATCH v4 10/19] target/loongarch: Use MMUConext in loongarch_map_tlb_entry() Bibo Mao
` (9 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
Function loongarch_check_pte() can get physical address and access
priviledge, it works on both TLB entry and pte entry. It can be used
in function loongarch_page_table_walker() also.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/cpu_helper.c | 42 +++++++++++++----------------------
1 file changed, 16 insertions(+), 26 deletions(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 5b140316bc..2cd43cd51d 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -106,15 +106,17 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
}
static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
- hwaddr *physical,
- int *prot, vaddr address)
+ MMUContext *context,
+ int access_type, int mmu_idx)
{
CPUState *cs = env_cpu(env);
target_ulong index, phys;
uint64_t dir_base, dir_width;
uint64_t base;
int level;
+ vaddr address;
+ address = context->addr;
if ((address >> 63) & 0x1) {
base = env->CSR_PGDH;
} else {
@@ -156,29 +158,9 @@ static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
base = ldq_phys(cs->as, phys);
}
- /* TODO: check plv and other bits? */
-
- /* base is pte, in normal pte format */
- if (!FIELD_EX64(base, TLBENTRY, V)) {
- return TLBRET_NOMATCH;
- }
-
- if (!FIELD_EX64(base, TLBENTRY, D)) {
- *prot = PAGE_READ;
- } else {
- *prot = PAGE_READ | PAGE_WRITE;
- }
-
- /* get TARGET_PAGE_SIZE aligned physical address */
- base += (address & TARGET_PHYS_MASK) & ((1 << dir_base) - 1);
- /* mask RPLV, NX, NR bits */
- base = FIELD_DP64(base, TLBENTRY_64, RPLV, 0);
- base = FIELD_DP64(base, TLBENTRY_64, NX, 0);
- base = FIELD_DP64(base, TLBENTRY_64, NR, 0);
- /* mask other attribute bits */
- *physical = base & TARGET_PAGE_MASK;
-
- return TLBRET_MATCH;
+ context->ps = dir_base;
+ context->pte = base;
+ return loongarch_check_pte(env, context, access_type, mmu_idx);
}
static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
@@ -187,7 +169,9 @@ static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
int is_debug)
{
TLBRet ret;
+ MMUContext context;
+ context.addr = address;
if (tcg_enabled()) {
ret = loongarch_get_addr_from_tlb(env, physical, prot, address,
access_type, mmu_idx);
@@ -202,7 +186,13 @@ static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
* legal mapping, even if the mapping is not yet in TLB. return 0 if
* there is a valid map, else none zero.
*/
- return loongarch_page_table_walker(env, physical, prot, address);
+ ret = loongarch_page_table_walker(env, &context, access_type, mmu_idx);
+ if (ret == TLBRET_MATCH) {
+ *physical = context.physical;
+ *prot = context.prot;
+ }
+
+ return ret;
}
return TLBRET_NOMATCH;
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 10/19] target/loongarch: Use MMUConext in loongarch_map_tlb_entry()
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (8 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 09/19] target/loongarch: Use loongarch_check_pte in loongarch_page_table_walker Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 5:57 ` Richard Henderson
2025-07-30 3:01 ` [PATCH v4 11/19] target/loongarch: Use MMUContext in loongarch_get_addr_from_tlb Bibo Mao
` (8 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function loongarch_map_tlb_entry(), parameter MMUConext is added
and remove parameter physical, prot and address.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 33 +++++++++++++++----------------
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 10322da62e..703ab9c8ca 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -648,28 +648,19 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,
env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
}
-static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
- int *prot, vaddr address,
+static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
+ MMUContext *context,
MMUAccessType access_type, int index,
int mmu_idx)
{
LoongArchTLB *tlb = &env->tlb[index];
uint8_t tlb_ps, n;
- MMUContext context;
- TLBRet ret;
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
- n = (address >> tlb_ps) & 0x1;/* Odd or even */
- context.pte = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
- context.addr = address;
- context.ps = tlb_ps;
- ret = loongarch_check_pte(env, &context, access_type, mmu_idx);
- if (ret == TLBRET_MATCH) {
- *physical = context.physical;
- *prot = context.prot;
- }
-
- return ret;
+ n = (context->addr >> tlb_ps) & 0x1;/* Odd or even */
+ context->pte = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
+ context->ps = tlb_ps;
+ return loongarch_check_pte(env, context, access_type, mmu_idx);
}
TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
@@ -677,11 +668,19 @@ TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
MMUAccessType access_type, int mmu_idx)
{
int index, match;
+ MMUContext context;
+ TLBRet ret;
+ context.addr = address;
match = loongarch_tlb_search(env, address, &index);
if (match) {
- return loongarch_map_tlb_entry(env, physical, prot,
- address, access_type, index, mmu_idx);
+ ret = loongarch_map_tlb_entry(env, &context, access_type, index,
+ mmu_idx);
+ if (ret == TLBRET_MATCH) {
+ *physical = context.physical;
+ *prot = context.prot;
+ }
+ return ret;
}
return TLBRET_NOMATCH;
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 11/19] target/loongarch: Use MMUContext in loongarch_get_addr_from_tlb
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (9 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 10/19] target/loongarch: Use MMUConext in loongarch_map_tlb_entry() Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 5:58 ` Richard Henderson
2025-07-30 3:01 ` [PATCH v4 12/19] target/loongarch: Use MMUContext in loongarch_map_address() Bibo Mao
` (7 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function loongarch_get_addr_from_tlb(), parameter MMUContext
is added and remove parameter physical, prot and address.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu_helper.c | 7 +++++--
target/loongarch/tcg/tcg_loongarch.h | 4 ++--
target/loongarch/tcg/tlb_helper.c | 18 +++++-------------
3 files changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 2cd43cd51d..51d77d7fcc 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -173,9 +173,12 @@ static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
context.addr = address;
if (tcg_enabled()) {
- ret = loongarch_get_addr_from_tlb(env, physical, prot, address,
- access_type, mmu_idx);
+ ret = loongarch_get_addr_from_tlb(env, &context, access_type, mmu_idx);
if (ret != TLBRET_NOMATCH) {
+ if (ret == TLBRET_MATCH) {
+ *physical = context.physical;
+ *prot = context.prot;
+ }
return ret;
}
}
diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tcg_loongarch.h
index 488700c3c3..47702893e3 100644
--- a/target/loongarch/tcg/tcg_loongarch.h
+++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -15,8 +15,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
- int *prot, target_ulong address,
+TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env,
+ MMUContext *context,
MMUAccessType access_type, int mmu_idx);
#endif /* TARGET_LOONGARCH_TCG_LOONGARCH_H */
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 703ab9c8ca..64a4e82dec 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -663,24 +663,16 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
return loongarch_check_pte(env, context, access_type, mmu_idx);
}
-TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical,
- int *prot, vaddr address,
+TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env,
+ MMUContext *context,
MMUAccessType access_type, int mmu_idx)
{
int index, match;
- MMUContext context;
- TLBRet ret;
- context.addr = address;
- match = loongarch_tlb_search(env, address, &index);
+ match = loongarch_tlb_search(env, context->addr, &index);
if (match) {
- ret = loongarch_map_tlb_entry(env, &context, access_type, index,
- mmu_idx);
- if (ret == TLBRET_MATCH) {
- *physical = context.physical;
- *prot = context.prot;
- }
- return ret;
+ return loongarch_map_tlb_entry(env, context, access_type, index,
+ mmu_idx);
}
return TLBRET_NOMATCH;
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 12/19] target/loongarch: Use MMUContext in loongarch_map_address()
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (10 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 11/19] target/loongarch: Use MMUContext in loongarch_get_addr_from_tlb Bibo Mao
@ 2025-07-30 3:01 ` Bibo Mao
2025-07-30 6:06 ` Richard Henderson
2025-07-30 3:08 ` [PATCH v4 13/19] target/loongarch: Use MMUContext in get_physical_address() Bibo Mao
` (6 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:01 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function loongarch_map_address(), parameter MMUContext is added
and remove parameter address, prot and address.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu_helper.c | 32 ++++++++++++++------------------
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 51d77d7fcc..dbc48aa9d4 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -163,22 +163,16 @@ static TLBRet loongarch_page_table_walker(CPULoongArchState *env,
return loongarch_check_pte(env, context, access_type, mmu_idx);
}
-static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, vaddr address,
+static TLBRet loongarch_map_address(CPULoongArchState *env,
+ MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug)
{
TLBRet ret;
- MMUContext context;
- context.addr = address;
if (tcg_enabled()) {
- ret = loongarch_get_addr_from_tlb(env, &context, access_type, mmu_idx);
+ ret = loongarch_get_addr_from_tlb(env, context, access_type, mmu_idx);
if (ret != TLBRET_NOMATCH) {
- if (ret == TLBRET_MATCH) {
- *physical = context.physical;
- *prot = context.prot;
- }
return ret;
}
}
@@ -189,13 +183,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
* legal mapping, even if the mapping is not yet in TLB. return 0 if
* there is a valid map, else none zero.
*/
- ret = loongarch_page_table_walker(env, &context, access_type, mmu_idx);
- if (ret == TLBRET_MATCH) {
- *physical = context.physical;
- *prot = context.prot;
- }
-
- return ret;
+ return loongarch_page_table_walker(env, context, access_type, mmu_idx);
}
return TLBRET_NOMATCH;
@@ -223,6 +211,8 @@ TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
+ MMUContext context;
+ TLBRet ret;
/* Check PG and DA */
if (da & !pg) {
@@ -258,8 +248,14 @@ TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
}
/* Mapped address */
- return loongarch_map_address(env, physical, prot, address,
- access_type, mmu_idx, is_debug);
+ context.addr = address;
+ ret = loongarch_map_address(env, &context,
+ access_type, mmu_idx, is_debug);
+ if (ret == TLBRET_MATCH) {
+ *physical = context.physical;
+ *prot = context.prot;
+ }
+ return ret;
}
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 13/19] target/loongarch: Use MMUContext in get_physical_address()
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (11 preceding siblings ...)
2025-07-30 3:01 ` [PATCH v4 12/19] target/loongarch: Use MMUContext in loongarch_map_address() Bibo Mao
@ 2025-07-30 3:08 ` Bibo Mao
2025-07-30 6:09 ` Richard Henderson
2025-07-30 3:10 ` [PATCH v4 14/19] target/loongarch: Track user space address accessed in kernel mode Bibo Mao
` (5 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:08 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function get_physical_address(), parameter MMUContext is added
and remove parameter address, prot and address.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu-mmu.h | 3 +--
target/loongarch/cpu_helper.c | 32 ++++++++++++-------------------
target/loongarch/tcg/tlb_helper.c | 8 +++++---
3 files changed, 18 insertions(+), 25 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index be3d11d3c1..0068d22efc 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -30,8 +30,7 @@ typedef struct MMUContext {
bool check_ps(CPULoongArchState *ent, uint8_t ps);
TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx);
-TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, vaddr address,
+TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug);
void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index dbc48aa9d4..ec84fb5425 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -200,8 +200,7 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, target_ulong dmw)
}
}
-TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
- int *prot, vaddr address,
+TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug)
{
@@ -211,13 +210,13 @@ TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);
uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
- MMUContext context;
- TLBRet ret;
+ vaddr address;
/* Check PG and DA */
+ address = context->addr;
if (da & !pg) {
- *physical = address & TARGET_PHYS_MASK;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ context->physical = address & TARGET_PHYS_MASK;
+ context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
@@ -235,8 +234,8 @@ TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
}
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
- *physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ context->physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
+ context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
}
@@ -248,25 +247,18 @@ TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical,
}
/* Mapped address */
- context.addr = address;
- ret = loongarch_map_address(env, &context,
- access_type, mmu_idx, is_debug);
- if (ret == TLBRET_MATCH) {
- *physical = context.physical;
- *prot = context.prot;
- }
- return ret;
+ return loongarch_map_address(env, context, access_type, mmu_idx, is_debug);
}
hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
CPULoongArchState *env = cpu_env(cs);
- hwaddr phys_addr;
- int prot;
+ MMUContext context;
- if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
+ context.addr = addr;
+ if (get_physical_address(env, &context, MMU_DATA_LOAD,
cpu_mmu_index(cs, false), 1) != TLBRET_MATCH) {
return -1;
}
- return phys_addr;
+ return context.physical;
}
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 64a4e82dec..7d3f98633d 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -517,13 +517,15 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPULoongArchState *env = cpu_env(cs);
hwaddr physical;
int prot;
+ MMUContext context;
TLBRet ret;
/* Data access */
- ret = get_physical_address(env, &physical, &prot, address,
- access_type, mmu_idx, 0);
-
+ context.addr = address;
+ ret = get_physical_address(env, &context, access_type, mmu_idx, 0);
if (ret == TLBRET_MATCH) {
+ physical = context.physical;
+ prot = context.prot;
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 14/19] target/loongarch: Track user space address accessed in kernel mode
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (12 preceding siblings ...)
2025-07-30 3:08 ` [PATCH v4 13/19] target/loongarch: Use MMUContext in get_physical_address() Bibo Mao
@ 2025-07-30 3:10 ` Bibo Mao
2025-07-30 3:10 ` [PATCH v4 15/19] target/loongarch: Use correct address when flush tlb Bibo Mao
` (4 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:10 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
The concept of mmu idx between QEMU TLB and LoongArch TLB emulation
is different:
mmu idx in QEMU TLB comes from currently working mode of vCPU
mmu idx from LoongArch TLB is page priviledge level
With copy_from_user() executed in system, vCPU is in kernel mode
however PLV of PTE is user mode.
Here field KM is added in LoongArch TLB entry to track whether the
lo0/lo1 pte entry is accessed in kernel mode. If set, when LoongArch
TLB is flushed, need flush QEMU TLB with mmu idx MMU_KERNEL_IDX.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/cpu-mmu.h | 2 ++
target/loongarch/cpu.h | 14 ++++++++++++++
target/loongarch/cpu_helper.c | 3 +++
target/loongarch/tcg/tlb_helper.c | 26 ++++++++++++++++++++++++++
4 files changed, 45 insertions(+)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index 0068d22efc..311bf7b2d7 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -25,6 +25,8 @@ typedef struct MMUContext {
hwaddr physical;
int ps; /* page size shift */
int prot;
+ int tlb_index;
+ int mmu_index;
} MMUContext;
bool check_ps(CPULoongArchState *ent, uint8_t ps);
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 7731f6acdc..3c5fcaa154 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -253,6 +253,20 @@ FIELD(TLB_MISC, E, 0, 1)
FIELD(TLB_MISC, ASID, 1, 10)
FIELD(TLB_MISC, VPPN, 13, 35)
FIELD(TLB_MISC, PS, 48, 6)
+/*
+ * Used by QEMU software, concept of mmu idx between QEMU TLB and LoongArch
+ * TLB emulation is different:
+ * mmu idx in QEMU TLB is current working mode of vCPU
+ * mmu idx in LoongArch TLB is PLV access level
+ * When funtion copy_from_user() executed with system emulation method,
+ * vCPU is in kernel mode however accessed address is user memory space.
+ *
+ * TLB lo0/lo1 entry mask with PLV MMU_USER_IDX accessed in kernel mode
+ */
+FIELD(TLB_MISC, KM, 54, 2)
+#define TLB_MISC_KM_PTE(n) BIT_ULL(R_TLB_MISC_KM_SHIFT + n)
+#define TLB_MISC_KM_PTE_LOW0 TLB_MISC_KM_PTE(0)
+#define TLB_MISC_KM_PTE_LOW1 TLB_MISC_KM_PTE(1)
#define LSX_LEN (128)
#define LASX_LEN (256)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index ec84fb5425..8831c95549 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -96,6 +96,7 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
context->physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
(context->addr & MAKE_64BIT_MASK(0, tlb_ps));
context->prot = PAGE_READ;
+ context->mmu_index = tlb_plv;
if (tlb_d) {
context->prot |= PAGE_WRITE;
}
@@ -217,6 +218,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
if (da & !pg) {
context->physical = address & TARGET_PHYS_MASK;
context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ context->mmu_index = MMU_DA_IDX;
return TLBRET_MATCH;
}
@@ -236,6 +238,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
context->physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ context->mmu_index = MMU_DA_IDX;
return TLBRET_MATCH;
}
}
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 7d3f98633d..d86a189239 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -172,6 +172,7 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
}
/* Store page size in field PS */
+ tlb->tlb_misc = 0;
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps);
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn);
tlb->tlb_misc = FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1);
@@ -510,6 +511,24 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
tlb_flush(env_cpu(env));
}
+/*
+ * Record tlb entry with virtual address from user mode accessed from
+ * vCPU kernel mode.
+ *
+ * If set, when LoongArch TLB is flushed, need flush QEMU TLB with mmu
+ * idx MMU_KERNEL_IDX
+ */
+static inline void tlb_set_accessed(CPULoongArchState *env, vaddr address,
+ int index)
+{
+ LoongArchTLB *tlb = &env->tlb[index];
+ uint8_t tlb_ps, n;
+
+ tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
+ n = (address >> tlb_ps) & 0x1;/* Odd or even */
+ tlb->tlb_misc |= TLB_MISC_KM_PTE(n);
+}
+
bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -529,6 +548,12 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
+
+ /* user mode address space is accessed in vCPU kernel mode */
+ if (mmu_idx == MMU_KERNEL_IDX && context.mmu_index == MMU_USER_IDX) {
+ tlb_set_accessed(env, address, context.tlb_index);
+ }
+
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx
" prot %d\n", __func__, address, physical, prot);
@@ -662,6 +687,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
n = (context->addr >> tlb_ps) & 0x1;/* Odd or even */
context->pte = n ? tlb->tlb_entry1 : tlb->tlb_entry0;
context->ps = tlb_ps;
+ context->tlb_index = index;
return loongarch_check_pte(env, context, access_type, mmu_idx);
}
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 15/19] target/loongarch: Use correct address when flush tlb
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (13 preceding siblings ...)
2025-07-30 3:10 ` [PATCH v4 14/19] target/loongarch: Track user space address accessed in kernel mode Bibo Mao
@ 2025-07-30 3:10 ` Bibo Mao
2025-07-30 6:12 ` Richard Henderson
2025-07-30 3:11 ` [PATCH v4 16/19] target/loongarch: Use mmu idx bitmap method " Bibo Mao
` (3 subsequent siblings)
18 siblings, 1 reply; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:10 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit.
However on LoongArch TLB emulation system, virtual address is
48 bit. It is necessary to signed-extend 48 bit address to 64 bit when
flush tlb, also fix address calculation issue with odd page.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index d86a189239..cf661aaeff 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -115,16 +115,16 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
pagesize = MAKE_64BIT_MASK(tlb_ps, 1);
mask = MAKE_64BIT_MASK(0, tlb_ps + 1);
+ addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask;
+ addr = sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS);
if (tlb_v0) {
- addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; /* even */
tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
mmu_idx, TARGET_LONG_BITS);
}
if (tlb_v1) {
- addr = (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & pagesize; /* odd */
- tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
+ tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize,
mmu_idx, TARGET_LONG_BITS);
}
}
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [PATCH v4 15/19] target/loongarch: Use correct address when flush tlb
2025-07-30 3:10 ` [PATCH v4 15/19] target/loongarch: Use correct address when flush tlb Bibo Mao
@ 2025-07-30 6:12 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2025-07-30 6:12 UTC (permalink / raw)
To: Bibo Mao, Song Gao; +Cc: Jiaxun Yang, qemu-devel
On 7/29/25 17:10, Bibo Mao wrote:
> With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit.
> However on LoongArch TLB emulation system, virtual address is
> 48 bit. It is necessary to signed-extend 48 bit address to 64 bit when
> flush tlb, also fix address calculation issue with odd page.
>
> Signed-off-by: Bibo Mao<maobibo@loongson.cn>
> ---
> target/loongarch/tcg/tlb_helper.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v4 16/19] target/loongarch: Use mmu idx bitmap method when flush tlb
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (14 preceding siblings ...)
2025-07-30 3:10 ` [PATCH v4 15/19] target/loongarch: Use correct address when flush tlb Bibo Mao
@ 2025-07-30 3:11 ` Bibo Mao
2025-07-30 3:11 ` [PATCH v4 17/19] target/loongarch: Add parameter tlb pointer with fill_tlb_entry Bibo Mao
` (2 subsequent siblings)
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:11 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With API tlb_flush_range_by_mmuidx(), bitmap of mmu idx should be used
rather than itself. And mmu idx comes from page table entry information
rather current running mode.
Also field KM in TLB misc records bitmap mask of TLB entry which is
access in kernel mode. If set, MMU_KERNEL_IDX should be added to
flush tlb.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index cf661aaeff..da2618ec62 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -101,8 +101,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
target_ulong addr, mask, pagesize;
uint8_t tlb_ps;
LoongArchTLB *tlb = &env->tlb[index];
-
- int mmu_idx = cpu_mmu_index(env_cpu(env), false);
+ int mmu_idx;
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);
@@ -119,11 +118,21 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
addr = sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS);
if (tlb_v0) {
+ mmu_idx = BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV));
+ /* Even page is accessed in kernel mode */
+ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW0) {
+ mmu_idx |= BIT(MMU_KERNEL_IDX);
+ }
tlb_flush_range_by_mmuidx(env_cpu(env), addr, pagesize,
mmu_idx, TARGET_LONG_BITS);
}
if (tlb_v1) {
+ mmu_idx = BIT(FIELD_EX64(tlb->tlb_entry1, TLBENTRY, PLV));
+ /* Odd page is accessed in kernel mode */
+ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW1) {
+ mmu_idx |= BIT(MMU_KERNEL_IDX);
+ }
tlb_flush_range_by_mmuidx(env_cpu(env), addr + pagesize, pagesize,
mmu_idx, TARGET_LONG_BITS);
}
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 17/19] target/loongarch: Add parameter tlb pointer with fill_tlb_entry
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (15 preceding siblings ...)
2025-07-30 3:11 ` [PATCH v4 16/19] target/loongarch: Use mmu idx bitmap method " Bibo Mao
@ 2025-07-30 3:11 ` Bibo Mao
2025-07-30 3:12 ` [PATCH v4 18/19] target/loongarch: Reduce TLB flush with helper_tlbwr Bibo Mao
2025-07-30 3:13 ` [PATCH v4 19/19] target/loongarch: Update TLB index selection method Bibo Mao
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:11 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function fill_tlb_entry(), it will update LoongArch emulated
TLB information. Here parameter tlb pointer is added so that TLB
entry will be updated based on relative TLB CSR registers.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/tcg/tlb_helper.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index da2618ec62..888a008944 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -153,9 +153,8 @@ static void invalidate_tlb(CPULoongArchState *env, int index)
invalidate_tlb_entry(env, index);
}
-static void fill_tlb_entry(CPULoongArchState *env, int index)
+static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb)
{
- LoongArchTLB *tlb = &env->tlb[index];
uint64_t lo0, lo1, csr_vppn;
uint16_t csr_asid;
uint8_t csr_ps;
@@ -323,7 +322,7 @@ void helper_tlbwr(CPULoongArchState *env)
return;
}
- fill_tlb_entry(env, index);
+ fill_tlb_entry(env, env->tlb + index);
}
void helper_tlbfill(CPULoongArchState *env)
@@ -361,7 +360,7 @@ void helper_tlbfill(CPULoongArchState *env)
}
invalidate_tlb(env, index);
- fill_tlb_entry(env, index);
+ fill_tlb_entry(env, env->tlb + index);
}
void helper_tlbclr(CPULoongArchState *env)
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 18/19] target/loongarch: Reduce TLB flush with helper_tlbwr
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (16 preceding siblings ...)
2025-07-30 3:11 ` [PATCH v4 17/19] target/loongarch: Add parameter tlb pointer with fill_tlb_entry Bibo Mao
@ 2025-07-30 3:12 ` Bibo Mao
2025-07-30 3:13 ` [PATCH v4 19/19] target/loongarch: Update TLB index selection method Bibo Mao
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:12 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function helper_tlbwr(), specified LoongArch TLB entry will be
updated. There are two PTE pages in one TLB entry, it is not
necessary to flush QEMU TLB when one PTE page keeps unchanged and
ther other PTE page is newly added.
Here check whether PTE page is the same or not, TLB flush can be
skipped if both are the same or newly added.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 33 ++++++++++++++++++++++++++-----
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 888a008944..0013810c50 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -313,16 +313,39 @@ void helper_tlbrd(CPULoongArchState *env)
void helper_tlbwr(CPULoongArchState *env)
{
int index = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, INDEX);
+ LoongArchTLB *old, new;
+ bool skip_inv = false;
+ uint8_t tlb_v0, tlb_v1;
- invalidate_tlb(env, index);
-
+ old = env->tlb + index;
if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) {
- env->tlb[index].tlb_misc = FIELD_DP64(env->tlb[index].tlb_misc,
- TLB_MISC, E, 0);
+ invalidate_tlb(env, index);
+ old->tlb_misc = FIELD_DP64(old->tlb_misc, TLB_MISC, E, 0);
return;
}
- fill_tlb_entry(env, env->tlb + index);
+ new.tlb_misc = 0;
+ new.tlb_entry0 = 0;
+ new.tlb_entry1 = 0;
+ fill_tlb_entry(env, &new);
+ /* Check whether ASID/VPPN is the same */
+ if (old->tlb_misc == new.tlb_misc) {
+ /* Check whether pte is the same or invalid */
+ tlb_v0 = FIELD_EX64(old->tlb_entry0, TLBENTRY, V);
+ tlb_v1 = FIELD_EX64(old->tlb_entry1, TLBENTRY, V);
+ if ((!tlb_v0 || new.tlb_entry0 == old->tlb_entry0) &&
+ (!tlb_v1 || new.tlb_entry1 == old->tlb_entry1)) {
+ skip_inv = true;
+ }
+ }
+
+ /* flush tlb before updating the entry */
+ if (!skip_inv) {
+ invalidate_tlb(env, index);
+ }
+ old->tlb_misc = new.tlb_misc;
+ old->tlb_entry0 = new.tlb_entry0;
+ old->tlb_entry1 = new.tlb_entry1;
}
void helper_tlbfill(CPULoongArchState *env)
--
2.39.3
^ permalink raw reply related [flat|nested] 36+ messages in thread* [PATCH v4 19/19] target/loongarch: Update TLB index selection method
2025-07-30 3:01 [PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu Bibo Mao
` (17 preceding siblings ...)
2025-07-30 3:12 ` [PATCH v4 18/19] target/loongarch: Reduce TLB flush with helper_tlbwr Bibo Mao
@ 2025-07-30 3:13 ` Bibo Mao
18 siblings, 0 replies; 36+ messages in thread
From: Bibo Mao @ 2025-07-30 3:13 UTC (permalink / raw)
To: Song Gao, Richard Henderson; +Cc: Jiaxun Yang, qemu-devel
With function helper_tlbfill(), since there is no suitable TLB entry,
new TLB will be added and invalidate one old TLB entry. The old TLB
entry index is selected randomly, instead it can be optimized as
following:
1. invalid TLB entry can be selected at first.
2. TLB entry with other ASID can be selected secondly
3. random method is used by last.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
target/loongarch/tcg/tlb_helper.c | 49 ++++++++++++++++++++++++++-----
1 file changed, 42 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 0013810c50..0a86040c41 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -351,8 +351,11 @@ void helper_tlbwr(CPULoongArchState *env)
void helper_tlbfill(CPULoongArchState *env)
{
uint64_t address, entryhi;
- int index, set, stlb_idx;
+ int index, set, i, stlb_idx;
uint16_t pagesize, stlb_ps;
+ uint16_t asid, tlb_asid;
+ LoongArchTLB *tlb;
+ uint8_t tlb_e;
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
entryhi = env->CSR_TLBREHI;
@@ -366,20 +369,52 @@ void helper_tlbfill(CPULoongArchState *env)
/* Validity of stlb_ps is checked in helper_csrwr_stlbps() */
stlb_ps = FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS);
+ asid = FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID);
if (pagesize == stlb_ps) {
/* Only write into STLB bits [47:13] */
address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
-
- /* Choose one set ramdomly */
- set = get_random_tlb(0, 7);
-
- /* Index in one set */
+ set = -1;
stlb_idx = (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */
+ for (i = 0; i < 8; ++i) {
+ tlb = &env->tlb[i * 256 + stlb_idx];
+ tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+ if (!tlb_e) {
+ set = i;
+ break;
+ }
+
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ if (asid != tlb_asid) {
+ set = i;
+ }
+ }
+ /* Choose one set randomly */
+ if (set < 0) {
+ set = get_random_tlb(0, 7);
+ }
index = set * 256 + stlb_idx;
} else {
/* Only write into MTLB */
- index = get_random_tlb(LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
+ index = -1;
+ for (i = LOONGARCH_STLB; i < LOONGARCH_TLB_MAX; i++) {
+ tlb = &env->tlb[i];
+ tlb_e = FIELD_EX64(tlb->tlb_misc, TLB_MISC, E);
+
+ if (!tlb_e) {
+ index = i;
+ break;
+ }
+
+ tlb_asid = FIELD_EX64(tlb->tlb_misc, TLB_MISC, ASID);
+ if (asid != tlb_asid) {
+ index = i;
+ }
+ }
+
+ if (index < 0) {
+ index = get_random_tlb(LOONGARCH_STLB, LOONGARCH_TLB_MAX - 1);
+ }
}
invalidate_tlb(env, index);
--
2.39.3
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