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From: Richard Purdie <richard.purdie@linuxfoundation.org>
To: "Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-devel@nongnu.org, "Victor Kamensky" <kamensky@cisco.com>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Richard Henderson <rth@twiddle.net>,
	Khem Raj <raj.khem@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Subject: Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property
Date: Wed, 14 Oct 2020 08:26:14 +0100	[thread overview]
Message-ID: <1780b7f17f7638a019a314dc47ec6a38d26d3205.camel@linuxfoundation.org> (raw)
In-Reply-To: <b4818cf4-4598-b7ac-a640-145eaab57f7f@linaro.org>

On Tue, 2020-10-13 at 19:22 -0700, Richard Henderson wrote:
> On 10/13/20 4:11 PM, Richard Henderson wrote:
> > On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote:
> > > Yocto developers have expressed interest in running MIPS32
> > > CPU with custom number of TLB:
> > > https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html
> > > 
> > > Help them by making the number of TLB entries a CPU property,
> > > keeping our set of CPU definitions in sync with real hardware.
> > 
> > You mean keeping the 34kf model within qemu in sync, rather than
> > creating a
> > nonsense model that doesn't exist.
> > 
> > Question: is this cpu parameter useful for anything else?
> > 
> > Because the ideal solution for a CI loop is to use one of the mips
> > cpu models
> > that has the hw page table walker (CP0C3_PW).  Having qemu being
> > able to refill
> > the tlb itself is massively faster.
> > 
> > We do not currently implement a mips cpu that has the PW.  When I
> > downloaded
> 
> Bah, "mips32 cpu".
> 
> We do have the P5600 that does has it, though the code is wrapped up
> in TARGET_MIPS64.  I'll also note that the code could be better
> placed [*]
> 
> > (1) anyone know if the PW incompatible with mips32?
> 
> I've since found a copy of the mips32-pra in the wayback machine and
> have answered this as "no" -- PW is documented for mips32.
> 
> > (2) if not, was there any mips32 hw built with PW
> >     that we could model?
> 
> But I still don't know about this.
> 
> A further question for the Yocto folks: could you make use of a 64-
> bit kernel in testing a 32-bit userspace?

We run testing of 64 bit kernel with 64 bit userspace and 32 bit kernel
with 32 bit userspace, we've tested that for years. I know some of our
users do use 64 bit kernels with 32 bit userspace and we do limited
testing of that for multilib support.

I think we did try testing an R2 setup but found little performance
change and I think it may have been unreliable so we didn't make the
switch. We did move to 34kf relatively recently as that did perform
marginally better and matched qemu's recommendations.

We've also run into a lot of problems with 32 bit mips in general if we
go over 256MB memory since that seems to trigger highmem and hangs
regularly for us. We're working on infrastructure to save out those
hung VMs to help us debug such issues but don't have that yet. Its not
regular enough and we don't have the expertise to debug it properly as
yet unfortunately.

There is a question of how valid a 32 bit kernel is these days,
particularly given the memory issues we seem to run into there with
larger images.

Cheers,

Richard




  parent reply	other threads:[~2020-10-14  7:27 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-13 13:25 [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property Philippe Mathieu-Daudé
2020-10-13 13:25 ` [RFC PATCH 1/3] target/mips: Make cpu_mips_realize_env() propagate Error Philippe Mathieu-Daudé
2020-10-13 13:25 ` [RFC PATCH 2/3] target/mips: Store number of TLB entries in CPUMIPSState Philippe Mathieu-Daudé
2020-10-13 13:25 ` [RFC PATCH 3/3] target/mips: Make the number of TLB entries a CPU property Philippe Mathieu-Daudé
2020-10-14 10:20   ` Jiaxun Yang
2020-10-14 10:54     ` Philippe Mathieu-Daudé
2020-10-13 23:11 ` [RFC PATCH 0/3] " Richard Henderson
2020-10-14  2:22   ` Richard Henderson
2020-10-14  3:21     ` Victor Kamensky (kamensky) via
2020-10-14  7:26     ` Richard Purdie [this message]
2020-10-14  1:36 ` Victor Kamensky (kamensky)
2020-10-14  7:14   ` Richard Purdie
2020-10-14 14:53     ` Philippe Mathieu-Daudé
2020-10-14 20:20       ` Victor Kamensky (kamensky) via
2020-10-14 20:53         ` Khem Raj
2020-10-15 18:56           ` Victor Kamensky (kamensky) via
2020-10-16 17:19             ` Richard Henderson

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