* [PATCH 1/2] aspeed: Fix maximum number of spi controller
@ 2025-03-17 6:59 Troy Lee via
2025-03-17 6:59 ` [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers Troy Lee via
2025-03-18 12:22 ` [PATCH 1/2] aspeed: Fix maximum number of spi controller Cédric Le Goater
0 siblings, 2 replies; 6+ messages in thread
From: Troy Lee via @ 2025-03-17 6:59 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: yunlin.tang
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
maximum number of spi controller to 2, result in ehci[0] is being
overwritten in runtime.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f899356ed9..f069d17d16 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -42,7 +42,7 @@
#include "hw/char/serial-mm.h"
#include "hw/intc/arm_gicv3.h"
-#define ASPEED_SPIS_NUM 2
+#define ASPEED_SPIS_NUM 3
#define ASPEED_EHCIS_NUM 2
#define ASPEED_WDTS_NUM 8
#define ASPEED_CPUS_NUM 4
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers
2025-03-17 6:59 [PATCH 1/2] aspeed: Fix maximum number of spi controller Troy Lee via
@ 2025-03-17 6:59 ` Troy Lee via
2025-03-18 12:38 ` Cédric Le Goater
2025-04-23 6:58 ` Cédric Le Goater
2025-03-18 12:22 ` [PATCH 1/2] aspeed: Fix maximum number of spi controller Cédric Le Goater
1 sibling, 2 replies; 6+ messages in thread
From: Troy Lee via @ 2025-03-17 6:59 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: yunlin.tang
AST27x0 has 4 EHCI controllers, where each CPU and I/O die has 2
instances. This patch use existing TYPE_PLATFORM_EHCI. After wiring up
the EHCI controller, the ast2700a1-evb can find up to 4 USB EHCI
interfaces.
ehci-platform 12061000.usb: EHCI Host Controller
ehci-platform 12061000.usb: new USB bus registered, assigned bus number 2
ehci-platform 12063000.usb: EHCI Host Controller
ehci-platform 12063000.usb: new USB bus registered, assigned bus number 3
ehci-platform 12061000.usb: irq 88, io mem 0x12061000
ehci-platform 12063000.usb: irq 90, io mem 0x12063000
ehci-platform 14121000.usb: EHCI Host Controller
ehci-platform 14123000.usb: EHCI Host Controller
ehci-platform 12061000.usb: USB 2.0 started, EHCI 1.00
ehci-platform 14121000.usb: new USB bus registered, assigned bus number 5
ehci-platform 14123000.usb: new USB bus registered, assigned bus number 6
ehci-platform 14121000.usb: irq 91, io mem 0x14121000
ehci-platform 14123000.usb: irq 92, io mem 0x14123000
ehci-platform 12063000.usb: USB 2.0 started, EHCI 1.00
usb usb2: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
usb usb3: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
ehci-platform 14121000.usb: USB 2.0 started, EHCI 1.00
usb usb5: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
ehci-platform 14123000.usb: USB 2.0 started, EHCI 1.00
usb usb6: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
Note that, AST27x0A0 only has 2 EHCI controllers due to hw issue.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++++++++++++++++
include/hw/arm/aspeed_soc.h | 4 +++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index dce7255a2c..4ff4462ec1 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -25,6 +25,8 @@
static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_EHCI1] = 0x12061000,
+ [ASPEED_DEV_EHCI2] = 0x12063000,
[ASPEED_DEV_HACE] = 0x12070000,
[ASPEED_DEV_EMMC] = 0x12090000,
[ASPEED_DEV_INTC] = 0x12100000,
@@ -47,6 +49,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_ETH2] = 0x14060000,
[ASPEED_DEV_ETH3] = 0x14070000,
[ASPEED_DEV_SDHCI] = 0x14080000,
+ [ASPEED_DEV_EHCI3] = 0x14121000,
+ [ASPEED_DEV_EHCI4] = 0x14123000,
[ASPEED_DEV_ADC] = 0x14C00000,
[ASPEED_DEV_SCUIO] = 0x14C02000,
[ASPEED_DEV_GPIO] = 0x14C0B000,
@@ -91,6 +95,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
[ASPEED_DEV_TIMER7] = 22,
[ASPEED_DEV_TIMER8] = 23,
[ASPEED_DEV_DP] = 28,
+ [ASPEED_DEV_EHCI1] = 33,
+ [ASPEED_DEV_EHCI2] = 37,
[ASPEED_DEV_LPC] = 128,
[ASPEED_DEV_IBT] = 128,
[ASPEED_DEV_KCS] = 128,
@@ -137,6 +143,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
[ASPEED_DEV_TIMER7] = 22,
[ASPEED_DEV_TIMER8] = 23,
[ASPEED_DEV_DP] = 28,
+ [ASPEED_DEV_EHCI1] = 33,
+ [ASPEED_DEV_EHCI2] = 37,
[ASPEED_DEV_LPC] = 192,
[ASPEED_DEV_IBT] = 192,
[ASPEED_DEV_KCS] = 192,
@@ -212,6 +220,8 @@ static const int ast2700_gic132_gic196_intcmap[] = {
[ASPEED_DEV_UART10] = 16,
[ASPEED_DEV_UART11] = 17,
[ASPEED_DEV_UART12] = 18,
+ [ASPEED_DEV_EHCI3] = 28,
+ [ASPEED_DEV_EHCI4] = 29,
};
/* GICINT 133 */
@@ -434,6 +444,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
}
+ for (i = 0; i < sc->ehcis_num; i++) {
+ object_initialize_child(obj, "ehci[*]", &s->ehci[i],
+ TYPE_PLATFORM_EHCI);
+ }
+
snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
object_initialize_child(obj, "sdmc", &s->sdmc, typename);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
@@ -709,6 +724,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
}
+ /* EHCI */
+ for (i = 0; i < sc->ehcis_num; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ sc->memmap[ASPEED_DEV_EHCI1 + i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
+ }
+
/*
* SDMC - SDRAM Memory Controller
* The SDMC controller is unlocked at SPL stage.
@@ -900,6 +926,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
sc->silicon_rev = AST2700_A0_SILICON_REV;
sc->sram_size = 0x20000;
sc->spis_num = 3;
+ sc->ehcis_num = 2;
sc->wdts_num = 8;
sc->macs_num = 1;
sc->uarts_num = 13;
@@ -927,6 +954,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data)
sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->sram_size = 0x20000;
sc->spis_num = 3;
+ sc->ehcis_num = 4;
sc->wdts_num = 8;
sc->macs_num = 3;
sc->uarts_num = 13;
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f069d17d16..c1e80c8908 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -43,7 +43,7 @@
#include "hw/intc/arm_gicv3.h"
#define ASPEED_SPIS_NUM 3
-#define ASPEED_EHCIS_NUM 2
+#define ASPEED_EHCIS_NUM 4
#define ASPEED_WDTS_NUM 8
#define ASPEED_CPUS_NUM 4
#define ASPEED_MACS_NUM 4
@@ -192,6 +192,8 @@ enum {
ASPEED_DEV_SPI2,
ASPEED_DEV_EHCI1,
ASPEED_DEV_EHCI2,
+ ASPEED_DEV_EHCI3,
+ ASPEED_DEV_EHCI4,
ASPEED_DEV_VIC,
ASPEED_DEV_INTC,
ASPEED_DEV_INTCIO,
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] aspeed: Fix maximum number of spi controller
2025-03-17 6:59 [PATCH 1/2] aspeed: Fix maximum number of spi controller Troy Lee via
2025-03-17 6:59 ` [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers Troy Lee via
@ 2025-03-18 12:22 ` Cédric Le Goater
1 sibling, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2025-03-18 12:22 UTC (permalink / raw)
To: Troy Lee, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: yunlin.tang
On 3/17/25 07:59, Troy Lee wrote:
> Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
> A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
> maximum number of spi controller to 2, result in ehci[0] is being
> overwritten in runtime.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Fixes: 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f899356ed9..f069d17d16 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -42,7 +42,7 @@
> #include "hw/char/serial-mm.h"
> #include "hw/intc/arm_gicv3.h"
>
> -#define ASPEED_SPIS_NUM 2
> +#define ASPEED_SPIS_NUM 3
> #define ASPEED_EHCIS_NUM 2
> #define ASPEED_WDTS_NUM 8
> #define ASPEED_CPUS_NUM 4
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers
2025-03-17 6:59 ` [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers Troy Lee via
@ 2025-03-18 12:38 ` Cédric Le Goater
2025-03-19 1:26 ` Troy Lee
2025-04-23 6:58 ` Cédric Le Goater
1 sibling, 1 reply; 6+ messages in thread
From: Cédric Le Goater @ 2025-03-18 12:38 UTC (permalink / raw)
To: Troy Lee, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: yunlin.tang
On 3/17/25 07:59, Troy Lee wrote:
> AST27x0 has 4 EHCI controllers, where each CPU and I/O die has 2
> instances. This patch use existing TYPE_PLATFORM_EHCI. After wiring up
> the EHCI controller, the ast2700a1-evb can find up to 4 USB EHCI
> interfaces.
>
> ehci-platform 12061000.usb: EHCI Host Controller
> ehci-platform 12061000.usb: new USB bus registered, assigned bus number 2
> ehci-platform 12063000.usb: EHCI Host Controller
> ehci-platform 12063000.usb: new USB bus registered, assigned bus number 3
> ehci-platform 12061000.usb: irq 88, io mem 0x12061000
> ehci-platform 12063000.usb: irq 90, io mem 0x12063000
> ehci-platform 14121000.usb: EHCI Host Controller
> ehci-platform 14123000.usb: EHCI Host Controller
> ehci-platform 12061000.usb: USB 2.0 started, EHCI 1.00
> ehci-platform 14121000.usb: new USB bus registered, assigned bus number 5
> ehci-platform 14123000.usb: new USB bus registered, assigned bus number 6
> ehci-platform 14121000.usb: irq 91, io mem 0x14121000
> ehci-platform 14123000.usb: irq 92, io mem 0x14123000
> ehci-platform 12063000.usb: USB 2.0 started, EHCI 1.00
> usb usb2: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
> usb usb3: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
> ehci-platform 14121000.usb: USB 2.0 started, EHCI 1.00
> usb usb5: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
> ehci-platform 14123000.usb: USB 2.0 started, EHCI 1.00
> usb usb6: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
This is a custom image ? and not the SDK v09.05.
> Note that, AST27x0A0 only has 2 EHCI controllers due to hw issue.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++++++++++++++++
> include/hw/arm/aspeed_soc.h | 4 +++-
> 2 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index dce7255a2c..4ff4462ec1 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -25,6 +25,8 @@
>
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_SRAM] = 0x10000000,
> + [ASPEED_DEV_EHCI1] = 0x12061000,
> + [ASPEED_DEV_EHCI2] = 0x12063000,
> [ASPEED_DEV_HACE] = 0x12070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> [ASPEED_DEV_INTC] = 0x12100000,
> @@ -47,6 +49,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_ETH2] = 0x14060000,
> [ASPEED_DEV_ETH3] = 0x14070000,
> [ASPEED_DEV_SDHCI] = 0x14080000,
> + [ASPEED_DEV_EHCI3] = 0x14121000,
> + [ASPEED_DEV_EHCI4] = 0x14123000,
> [ASPEED_DEV_ADC] = 0x14C00000,
> [ASPEED_DEV_SCUIO] = 0x14C02000,
> [ASPEED_DEV_GPIO] = 0x14C0B000,
> @@ -91,6 +95,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
> [ASPEED_DEV_TIMER7] = 22,
> [ASPEED_DEV_TIMER8] = 23,
> [ASPEED_DEV_DP] = 28,
> + [ASPEED_DEV_EHCI1] = 33,
> + [ASPEED_DEV_EHCI2] = 37,
> [ASPEED_DEV_LPC] = 128,
> [ASPEED_DEV_IBT] = 128,
> [ASPEED_DEV_KCS] = 128,
> @@ -137,6 +143,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> [ASPEED_DEV_TIMER7] = 22,
> [ASPEED_DEV_TIMER8] = 23,
> [ASPEED_DEV_DP] = 28,
> + [ASPEED_DEV_EHCI1] = 33,
> + [ASPEED_DEV_EHCI2] = 37,
> [ASPEED_DEV_LPC] = 192,
> [ASPEED_DEV_IBT] = 192,
> [ASPEED_DEV_KCS] = 192,
> @@ -212,6 +220,8 @@ static const int ast2700_gic132_gic196_intcmap[] = {
> [ASPEED_DEV_UART10] = 16,
> [ASPEED_DEV_UART11] = 17,
> [ASPEED_DEV_UART12] = 18,
> + [ASPEED_DEV_EHCI3] = 28,
> + [ASPEED_DEV_EHCI4] = 29,
> };
>
> /* GICINT 133 */
> @@ -434,6 +444,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
> object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
> }
>
> + for (i = 0; i < sc->ehcis_num; i++) {
> + object_initialize_child(obj, "ehci[*]", &s->ehci[i],
> + TYPE_PLATFORM_EHCI);
> + }
> +
> snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
> object_initialize_child(obj, "sdmc", &s->sdmc, typename);
> object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
> @@ -709,6 +724,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
> }
>
> + /* EHCI */
> + for (i = 0; i < sc->ehcis_num; i++) {
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
> + return;
> + }
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
> + sc->memmap[ASPEED_DEV_EHCI1 + i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
> + aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
> + }
> +
> /*
> * SDMC - SDRAM Memory Controller
> * The SDMC controller is unlocked at SPL stage.
> @@ -900,6 +926,7 @@ static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
> sc->silicon_rev = AST2700_A0_SILICON_REV;
> sc->sram_size = 0x20000;
> sc->spis_num = 3;
> + sc->ehcis_num = 2;
> sc->wdts_num = 8;
> sc->macs_num = 1;
> sc->uarts_num = 13;
> @@ -927,6 +954,7 @@ static void aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data)
> sc->silicon_rev = AST2700_A1_SILICON_REV;
> sc->sram_size = 0x20000;
> sc->spis_num = 3;
> + sc->ehcis_num = 4;
> sc->wdts_num = 8;
> sc->macs_num = 3;
> sc->uarts_num = 13;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f069d17d16..c1e80c8908 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -43,7 +43,7 @@
> #include "hw/intc/arm_gicv3.h"
>
> #define ASPEED_SPIS_NUM 3
> -#define ASPEED_EHCIS_NUM 2
> +#define ASPEED_EHCIS_NUM 4
> #define ASPEED_WDTS_NUM 8
> #define ASPEED_CPUS_NUM 4
> #define ASPEED_MACS_NUM 4
> @@ -192,6 +192,8 @@ enum {
> ASPEED_DEV_SPI2,
> ASPEED_DEV_EHCI1,
> ASPEED_DEV_EHCI2,
> + ASPEED_DEV_EHCI3,
> + ASPEED_DEV_EHCI4,
> ASPEED_DEV_VIC,
> ASPEED_DEV_INTC,
> ASPEED_DEV_INTCIO,
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers
2025-03-18 12:38 ` Cédric Le Goater
@ 2025-03-19 1:26 ` Troy Lee
0 siblings, 0 replies; 6+ messages in thread
From: Troy Lee @ 2025-03-19 1:26 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Jamin Lin, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Yunlin Tang
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, March 18, 2025 8:39 PM
> To: Troy Lee <troy_lee@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Steven Lee <steven_lee@aspeedtech.com>; Troy
> Lee <leetroy@gmail.com>; Jamin Lin <jamin_lin@aspeedtech.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> here <qemu-devel@nongnu.org>
> Cc: Yunlin Tang <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers
>
> On 3/17/25 07:59, Troy Lee wrote:
> > AST27x0 has 4 EHCI controllers, where each CPU and I/O die has 2
> > instances. This patch use existing TYPE_PLATFORM_EHCI. After wiring up
> > the EHCI controller, the ast2700a1-evb can find up to 4 USB EHCI
> > interfaces.
> >
> > ehci-platform 12061000.usb: EHCI Host Controller ehci-platform
> > 12061000.usb: new USB bus registered, assigned bus number 2
> > ehci-platform 12063000.usb: EHCI Host Controller ehci-platform
> > 12063000.usb: new USB bus registered, assigned bus number 3
> > ehci-platform 12061000.usb: irq 88, io mem 0x12061000 ehci-platform
> > 12063000.usb: irq 90, io mem 0x12063000 ehci-platform 14121000.usb:
> > EHCI Host Controller ehci-platform 14123000.usb: EHCI Host Controller
> > ehci-platform 12061000.usb: USB 2.0 started, EHCI 1.00 ehci-platform
> > 14121000.usb: new USB bus registered, assigned bus number 5
> > ehci-platform 14123000.usb: new USB bus registered, assigned bus
> > number 6 ehci-platform 14121000.usb: irq 91, io mem 0x14121000
> > ehci-platform 14123000.usb: irq 92, io mem 0x14123000 ehci-platform
> > 12063000.usb: USB 2.0 started, EHCI 1.00 usb usb2: Manufacturer: Linux
> > 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd usb usb3:
> > Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty
> > ehci_hcd ehci-platform 14121000.usb: USB 2.0 started, EHCI 1.00 usb
> > usb5: Manufacturer: Linux
> > 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd ehci-platform
> > 14123000.usb: USB 2.0 started, EHCI 1.00 usb usb6: Manufacturer: Linux
> > 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
>
> This is a custom image ? and not the SDK v09.05.
>
Yes, this is a customized v09.05 image by enabling ehci0~ehci3 node
in Kernel device tree.
Thanks for reviewing.
> > Note that, AST27x0A0 only has 2 EHCI controllers due to hw issue.
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
>
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
>
> Thanks,
>
> C.
>
>
> > ---
> > hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++++++++++++++++
> > include/hw/arm/aspeed_soc.h | 4 +++-
> > 2 files changed, 31 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > dce7255a2c..4ff4462ec1 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -25,6 +25,8 @@
> >
> > static const hwaddr aspeed_soc_ast2700_memmap[] = {
> > [ASPEED_DEV_SRAM] = 0x10000000,
> > + [ASPEED_DEV_EHCI1] = 0x12061000,
> > + [ASPEED_DEV_EHCI2] = 0x12063000,
> > [ASPEED_DEV_HACE] = 0x12070000,
> > [ASPEED_DEV_EMMC] = 0x12090000,
> > [ASPEED_DEV_INTC] = 0x12100000,
> > @@ -47,6 +49,8 @@ static const hwaddr aspeed_soc_ast2700_memmap[]
> = {
> > [ASPEED_DEV_ETH2] = 0x14060000,
> > [ASPEED_DEV_ETH3] = 0x14070000,
> > [ASPEED_DEV_SDHCI] = 0x14080000,
> > + [ASPEED_DEV_EHCI3] = 0x14121000,
> > + [ASPEED_DEV_EHCI4] = 0x14123000,
> > [ASPEED_DEV_ADC] = 0x14C00000,
> > [ASPEED_DEV_SCUIO] = 0x14C02000,
> > [ASPEED_DEV_GPIO] = 0x14C0B000,
> > @@ -91,6 +95,8 @@ static const int aspeed_soc_ast2700a0_irqmap[] = {
> > [ASPEED_DEV_TIMER7] = 22,
> > [ASPEED_DEV_TIMER8] = 23,
> > [ASPEED_DEV_DP] = 28,
> > + [ASPEED_DEV_EHCI1] = 33,
> > + [ASPEED_DEV_EHCI2] = 37,
> > [ASPEED_DEV_LPC] = 128,
> > [ASPEED_DEV_IBT] = 128,
> > [ASPEED_DEV_KCS] = 128,
> > @@ -137,6 +143,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> > [ASPEED_DEV_TIMER7] = 22,
> > [ASPEED_DEV_TIMER8] = 23,
> > [ASPEED_DEV_DP] = 28,
> > + [ASPEED_DEV_EHCI1] = 33,
> > + [ASPEED_DEV_EHCI2] = 37,
> > [ASPEED_DEV_LPC] = 192,
> > [ASPEED_DEV_IBT] = 192,
> > [ASPEED_DEV_KCS] = 192,
> > @@ -212,6 +220,8 @@ static const int ast2700_gic132_gic196_intcmap[] =
> {
> > [ASPEED_DEV_UART10] = 16,
> > [ASPEED_DEV_UART11] = 17,
> > [ASPEED_DEV_UART12] = 18,
> > + [ASPEED_DEV_EHCI3] = 28,
> > + [ASPEED_DEV_EHCI4] = 29,
> > };
> >
> > /* GICINT 133 */
> > @@ -434,6 +444,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
> > object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
> > }
> >
> > + for (i = 0; i < sc->ehcis_num; i++) {
> > + object_initialize_child(obj, "ehci[*]", &s->ehci[i],
> > + TYPE_PLATFORM_EHCI);
> > + }
> > +
> > snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
> > object_initialize_child(obj, "sdmc", &s->sdmc, typename);
> > object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), @@
> > -709,6 +724,17 @@ static void aspeed_soc_ast2700_realize(DeviceState
> *dev, Error **errp)
> > ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
> > }
> >
> > + /* EHCI */
> > + for (i = 0; i < sc->ehcis_num; i++) {
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
> > + return;
> > + }
> > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
> > + sc->memmap[ASPEED_DEV_EHCI1 + i]);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
> > + aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
> > + }
> > +
> > /*
> > * SDMC - SDRAM Memory Controller
> > * The SDMC controller is unlocked at SPL stage.
> > @@ -900,6 +926,7 @@ static void
> aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
> > sc->silicon_rev = AST2700_A0_SILICON_REV;
> > sc->sram_size = 0x20000;
> > sc->spis_num = 3;
> > + sc->ehcis_num = 2;
> > sc->wdts_num = 8;
> > sc->macs_num = 1;
> > sc->uarts_num = 13;
> > @@ -927,6 +954,7 @@ static void
> aspeed_soc_ast2700a1_class_init(ObjectClass *oc, void *data)
> > sc->silicon_rev = AST2700_A1_SILICON_REV;
> > sc->sram_size = 0x20000;
> > sc->spis_num = 3;
> > + sc->ehcis_num = 4;
> > sc->wdts_num = 8;
> > sc->macs_num = 3;
> > sc->uarts_num = 13;
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index f069d17d16..c1e80c8908 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -43,7 +43,7 @@
> > #include "hw/intc/arm_gicv3.h"
> >
> > #define ASPEED_SPIS_NUM 3
> > -#define ASPEED_EHCIS_NUM 2
> > +#define ASPEED_EHCIS_NUM 4
> > #define ASPEED_WDTS_NUM 8
> > #define ASPEED_CPUS_NUM 4
> > #define ASPEED_MACS_NUM 4
> > @@ -192,6 +192,8 @@ enum {
> > ASPEED_DEV_SPI2,
> > ASPEED_DEV_EHCI1,
> > ASPEED_DEV_EHCI2,
> > + ASPEED_DEV_EHCI3,
> > + ASPEED_DEV_EHCI4,
> > ASPEED_DEV_VIC,
> > ASPEED_DEV_INTC,
> > ASPEED_DEV_INTCIO,
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers
2025-03-17 6:59 ` [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers Troy Lee via
2025-03-18 12:38 ` Cédric Le Goater
@ 2025-04-23 6:58 ` Cédric Le Goater
1 sibling, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2025-04-23 6:58 UTC (permalink / raw)
To: Troy Lee, Peter Maydell, Steven Lee, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: yunlin.tang
On 3/17/25 07:59, Troy Lee wrote:
> AST27x0 has 4 EHCI controllers, where each CPU and I/O die has 2
> instances. This patch use existing TYPE_PLATFORM_EHCI. After wiring up
> the EHCI controller, the ast2700a1-evb can find up to 4 USB EHCI
> interfaces.
>
> ehci-platform 12061000.usb: EHCI Host Controller
> ehci-platform 12061000.usb: new USB bus registered, assigned bus number 2
> ehci-platform 12063000.usb: EHCI Host Controller
> ehci-platform 12063000.usb: new USB bus registered, assigned bus number 3
> ehci-platform 12061000.usb: irq 88, io mem 0x12061000
> ehci-platform 12063000.usb: irq 90, io mem 0x12063000
> ehci-platform 14121000.usb: EHCI Host Controller
> ehci-platform 14123000.usb: EHCI Host Controller
> ehci-platform 12061000.usb: USB 2.0 started, EHCI 1.00
> ehci-platform 14121000.usb: new USB bus registered, assigned bus number 5
> ehci-platform 14123000.usb: new USB bus registered, assigned bus number 6
> ehci-platform 14121000.usb: irq 91, io mem 0x14121000
> ehci-platform 14123000.usb: irq 92, io mem 0x14123000
> ehci-platform 12063000.usb: USB 2.0 started, EHCI 1.00
> usb usb2: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
> usb usb3: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
> ehci-platform 14121000.usb: USB 2.0 started, EHCI 1.00
> usb usb5: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
> ehci-platform 14123000.usb: USB 2.0 started, EHCI 1.00
> usb usb6: Manufacturer: Linux 6.6.78-dirty-bafd2830c17c-gbafd2830c17c-dirty ehci_hcd
>
> Note that, AST27x0A0 only has 2 EHCI controllers due to hw issue.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Applied to aspeed-next.
Thanks,
C.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-04-23 6:59 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-17 6:59 [PATCH 1/2] aspeed: Fix maximum number of spi controller Troy Lee via
2025-03-17 6:59 ` [PATCH 2/2] hw/arm: ast27x0: Wire up EHCI controllers Troy Lee via
2025-03-18 12:38 ` Cédric Le Goater
2025-03-19 1:26 ` Troy Lee
2025-04-23 6:58 ` Cédric Le Goater
2025-03-18 12:22 ` [PATCH 1/2] aspeed: Fix maximum number of spi controller Cédric Le Goater
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