From: Thomas Huth <thuth@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] arm_gicv3: Fix broken logic in ELRSR calculation
Date: Thu, 26 Jan 2017 10:43:26 +0100 [thread overview]
Message-ID: <17aeed6e-77e8-4261-e697-28a26841ee60@redhat.com> (raw)
In-Reply-To: <1485255993-6322-1-git-send-email-peter.maydell@linaro.org>
On 24.01.2017 12:06, Peter Maydell wrote:
> Fix a broken expression in the calculation of ELRSR
> register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
> we want to check for != 0, because the HW bit is not
> bit 0 so a test for == 1 is always false.
>
> Fixes: https://bugs.launchpad.net/bugs/1658506
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gicv3_cpuif.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index a9ee7fd..c25ee03 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -2430,7 +2430,7 @@ static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> uint64_t lr = cs->ich_lr_el2[i];
>
> if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
> - ((lr & ICH_LR_EL2_HW) == 1 || (lr & ICH_LR_EL2_EOI) == 0)) {
> + ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) {
> value |= (1 << i);
> }
> }
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
prev parent reply other threads:[~2017-01-26 9:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-24 11:06 [Qemu-devel] [PATCH] arm_gicv3: Fix broken logic in ELRSR calculation Peter Maydell
2017-01-26 9:43 ` Thomas Huth [this message]
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