From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36529) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c2Ix7-0006vZ-FC for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:25:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c2Ix1-0000yl-Om for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:25:13 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53244) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c2Ix1-0000wu-IB for qemu-devel@nongnu.org; Thu, 03 Nov 2016 10:25:07 -0400 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 03 Nov 2016 08:25:05 -0600 From: cov@codeaurora.org In-Reply-To: <20161103103507.qg65rruprmm6drzk@kamzik.brq.redhat.com> References: <1478125337-11770-1-git-send-email-wei@redhat.com> <1478125337-11770-3-git-send-email-wei@redhat.com> <20161103103507.qg65rruprmm6drzk@kamzik.brq.redhat.com> Message-ID: <17b56cf125cf91f0effe8aacbc8df4d1@codeaurora.org> Subject: Re: [Qemu-devel] [kvm-unit-tests PATCHv7 2/3] arm: pmu: Check cycle count increases List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrew Jones Cc: Wei Huang , alindsay@codeaurora.org, kvm@vger.kernel.org, croberts@codeaurora.org, qemu-devel@nongnu.org, alistair.francis@xilinx.com, shannon.zhao@linaro.org, kvmarm@lists.cs.columbia.edu On 2016-11-03 04:35, Andrew Jones wrote: >> +/* >> + * Ensure that the cycle counter progresses between back-to-back >> reads. >> + */ >> +static bool check_cycles_increase(void) >> +{ >> + struct pmu_data pmu = {{0}}; >> + >> + enable_counter(ARMV8_PMU_CYCLE_IDX); >> + set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ >> + >> + pmu.enable = 1; >> + set_pmcr(pmu.pmcr_el0); >> + >> + for (int i = 0; i < NR_SAMPLES; i++) { >> + unsigned long a, b; >> + >> + a = get_pmccntr(); >> + b = get_pmccntr(); >> + >> + if (a >= b) { >> + printf("Read %ld then %ld.\n", a, b); >> + return false; >> + } >> + } >> + >> + pmu.enable = 0; >> + set_pmcr(pmu.pmcr_el0); >> + >> + return true; >> +} >> + >> int main(void) >> { >> report_prefix_push("pmu"); >> >> report("Control register", check_pmcr()); >> + report("Monotonically increasing cycle count", >> check_cycles_increase()); >> >> return report_summary(); >> } > > What happens with this test running on tcg? Do we just fail? Does it > explode? Is there a register we can probe and when it indicates things > won't work we can invoke a report_skip? A monotonically increasing value (but not any attempt at approximating actual cycle values) in cycle counter is pretty much the only piece of the PMU it's had implemented for the past while. We'll have to check whether TCG can handle the filter and enable set registers, but if it doesn't yet, that's something we can improve :). Thanks, Cov