From: Richard Henderson <richard.henderson@linaro.org>
To: Max Chou <max.chou@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions
Date: Thu, 25 Jul 2024 16:04:01 +1000 [thread overview]
Message-ID: <17b9f3cc-1ad7-4e79-8693-1f327f9bd5a6@linaro.org> (raw)
In-Reply-To: <20240717133936.713642-5-max.chou@sifive.com>
On 7/17/24 23:39, Max Chou wrote:
> +static inline QEMU_ALWAYS_INLINE void
> +vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host,
> + void *vd, uint32_t evl, uint32_t reg_start, void *host,
> + uint32_t esz, bool is_load)
> +{
> +#if TARGET_BIG_ENDIAN != HOST_BIG_ENDIAN
> + for (; reg_start < evl; reg_start++, host += esz) {
> + uint32_t byte_off = reg_start * esz;
> + ldst_host(vd, byte_off, host);
> + }
> +#else
> + uint32_t byte_offset = reg_start * esz;
> + uint32_t size = (evl - reg_start) * esz;
> +
> + if (is_load) {
> + memcpy(vd + byte_offset, host, size);
> + } else {
> + memcpy(host, vd + byte_offset, size);
> + }
> +#endif
First, TARGET_BIG_ENDIAN is always false, so this reduces to HOST_BIG_ENDIAN.
Second, even if TARGET_BIG_ENDIAN were true, this optimization would be wrong, because of
the element ordering given in vector_internals.h (i.e. H1 etc).
Third, this can be done with C if, instead of cpp ifdef, so that you always compile-test
both sides.
Fourth... what are the atomicity guarantees of RVV? I didn't immediately see anything in
the RVV manual, which suggests that the atomicity is the same as individual integer loads
of the same size. Because there are no atomicity guarantees for memcpy, you can only use
this for byte load/store.
For big-endian bytes, you can optimize this to 64-bit little-endian operations.
Compare arm gen_sve_ldr.
r~
next prev parent reply other threads:[~2024-07-25 6:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-17 13:39 [RFC PATCH v5 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions Max Chou
2024-07-17 13:39 ` [RFC PATCH v5 1/5] target/riscv: Set vdata.vm field for vector load/store whole register instructions Max Chou
2024-07-17 13:39 ` [RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store Max Chou
2024-07-25 5:51 ` Richard Henderson
2024-07-30 14:24 ` Max Chou
2024-07-17 13:39 ` [RFC PATCH v5 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store Max Chou
2024-07-17 13:39 ` [RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions Max Chou
2024-07-25 6:04 ` Richard Henderson [this message]
2024-07-30 15:16 ` Max Chou
2024-07-17 13:39 ` [RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance Max Chou
2024-07-25 6:05 ` Richard Henderson
2024-07-30 13:29 ` Max Chou
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