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[180.150.56.70]) by smtp.gmail.com with ESMTPSA id cp9-20020a170902e78900b0018700ba9090sm905387plb.185.2022.10.28.12.44.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Oct 2022 12:44:02 -0700 (PDT) Message-ID: <17d1bc6a-a30e-ee8c-b3c3-a74dce657375@linaro.org> Date: Sat, 29 Oct 2022 06:43:57 +1100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH 5/7] target/arm: Implement HCR_EL2.TICAB,TOCU traps Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20221028134002.730598-1-peter.maydell@linaro.org> <20221028134002.730598-6-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20221028134002.730598-6-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/29/22 00:40, Peter Maydell wrote: > For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS > and IC IALLUIS cache maintenance instructions. > > The HCR_EL2.TOCU bit traps all the other cache maintenance > instructions that operate to the point of unification: > AArch64 IC IVAU, IC IALLU, DC CVAU > AArch32 ICIMVAU, ICIALLU, DCCMVAU > > The two trap bits between them cover all of the cache maintenance > instructions which must also check the HCR_TPU flag. Turn the old > aa64_cacheop_pou_access() function into a helper function which takes > the set of HCR_EL2 flags to check as an argument, and call it from > new access_ticab() and access_tocu() functions as appropriate for > each cache op. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 36 +++++++++++++++++++++++------------- > 1 file changed, 23 insertions(+), 13 deletions(-) Reviewed-by: Richard Henderson r~