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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20689095700sm19620765ad.19.2024.09.03.07.51.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Sep 2024 07:51:34 -0700 (PDT) Message-ID: <181d95aa-9a2c-465b-b549-076572db601a@linaro.org> Date: Tue, 3 Sep 2024 07:51:31 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops From: Richard Henderson To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240830061607.1940-1-zhiwei_liu@linux.alibaba.com> <20240830061607.1940-9-zhiwei_liu@linux.alibaba.com> <629e9969-157e-4f58-b48f-52aea4c0c48f@linaro.org> Content-Language: en-US In-Reply-To: <629e9969-157e-4f58-b48f-52aea4c0c48f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/2/24 23:45, Richard Henderson wrote: > I think the first implementation should be simpler: > > CONST('C', TCG_CT_CONST_CMP_VI) > > tcg_target_const_match() > { >     ... >     if ((ct & TCG_CT_CONST_CMP_VI) && >         val >= tcg_cmpcond_to_rvv_vi[cond].min && >         val <= tcg_cmpcond_to_rvv_vi[cond].max) { >         return true; >     } > } > >     case INDEX_op_cmp_vec: >         riscv_set_vec_config_vl_vece(s, type, vece); >         cond = args[3]; >         if (c2) { >             tcg_out_opc_vi(s, tcg_cmpcond_to_rvv_vi[cond].op, a0, a1, >                            a2 - tcg_cmpcond_to_rvv_vi[cond].adjust); >         } else if (tcg_cmpcond_to_rvv_vv[cond].swap) { >             tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, a0, a2, a1); >         } else { >             tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, a0, a1, a2); >         } >         break; > > This appears to not require any expansion in tcg_expand_vec_op at all. I knew I should have slept on that answer. Of course you need expansion, because riscv cmp_vv produces a mask. However, I think we should simply model this as INDEX_op_cmpsel_vec: case INDEX_op_cmpsel_vec: riscv_set_vec_config_vl_vece(s, type, vece); a3 = args[3]; a4 = args[4]; cond = args[5]; /* Use only vmerge_vim if possible, by inverting the test. */ if (const_args[4] && !const_args[3]) { cond = tcg_cond_inv(cond); a3 = a4; a4 = args[3]; const_args[3] = true; const_args[4] = false; } /* Perform the comparison into V0 mask. */ if (const_args[2]) { tcg_out_opc_vi(s, tcg_cmpcond_to_rvv_vi[cond].op, TCG_REG_V0, a1, a2 - tcg_cmpcond_to_rvv_vi[cond].adjust); } else if (tcg_cmpcond_to_rvv_vv[cond].swap) { tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, TCG_REG_V0, a2, a1); } else { tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, TCG_REG_V0, a1, a2); } if (const_args[3]) { if (const_args[4]) { tcg_out_opc_vi(s, OPC_VMV_V_I, a0, TCG_REG_V0, a4, true); a4 = a0; } tcg_out_opc_vim_mask(s, OPC_VMERGE_VIM, a0, a3, a4); } else { tcg_out_opc_vvm_mask(s, OPC_VMERGE_VVM, a0, a3, a4); } break; Then INDEX_op_cmp_vec should be expanded to INDEX_op_cmpsel_vec a0, a1, a2, -1, 0, a3 r~