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[156.19.246.23]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2230a0944a4sm238125ad.121.2025.02.24.12.35.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Feb 2025 12:35:29 -0800 (PST) Message-ID: <1824fbe1-33a1-40db-8e9a-afc00f13d2b4@linaro.org> Date: Mon, 24 Feb 2025 12:35:26 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/61] target/arm: Implement FEAT_SME2 From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org References: <20250206195715.2150758-1-richard.henderson@linaro.org> <9e0853e9-b590-4a84-8214-fbb543bd4359@linaro.org> Content-Language: en-US In-Reply-To: <9e0853e9-b590-4a84-8214-fbb543bd4359@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/24/25 12:27, Richard Henderson wrote: > On 2/6/25 11:56, Richard Henderson wrote: >> Based-on:20250201164012.1660228-1-peter.maydell@linaro.org >> ("[PATCH v2 00/69] target/arm: FEAT_AFP and FEAT_RPRES") >> >> This implements the Scalar Matrix Extensions, version 2, plus two >> trivial extensions for float16 and bfloat16. >> >> This hasn't been tested much at all; I need to either get FVP up and >> running for RISU comparison, or write some stand-alone test cases. >> But in the meantime this could use some eyes. >> >> SME2 is the first vector-like extension we've had that has dynamic >> indexing of registers: ZArray[(rv + offset) % svl], where RV is a >> general register.  So the first thing I do is extend TCG's gvec >> support to handle TCGv_ptr base + offset addressing.  I only changed >> enough to handle what I needed within SME2; changing it all would be >> a big job, and it would (at least for the moment) remain unused. >> >> Still to-do are few more extensions for SME2p1. > > Ho hum.  I've missed the entire set of counted predicate insns. > Hooray for Arm sample code! Oh, duh -- they're in SME2p1, which is I guess not as optional as I assumed. r~