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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4587054f27dsm160707155e9.11.2025.07.28.08.52.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Jul 2025 08:52:27 -0700 (PDT) Message-ID: <187caaa6-ddc4-4e20-8c51-60bd7f254311@linaro.org> Date: Mon, 28 Jul 2025 17:52:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] hw/mips: Proper multi core support To: Jiaxun Yang , QEMU devel References: <20240506-mips-smp-v1-0-3cc234786910@flygoat.com> <632e091b-9af7-4363-8ce6-73cb6bde41b4@app.fastmail.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <632e091b-9af7-4363-8ce6-73cb6bde41b4@app.fastmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 15/7/25 21:08, Jiaxun Yang wrote: > > > 在2024年5月6日周一 下午4:31，Jiaxun Yang写道： >> Hi all, >> >> This series implemented propper multiple core support for MIPS >> CPS systsm. > > Ping :-) > > This is a really long outstanding series, I just want to get some > review before respin. Tagged for review, sorry I missed it... > > Thanks > Jiaxun > >> >> Previously all CPUs are being implemented as a smt thread in a >> single core. Now it respects topology supplied in QEMU args. >> >> To test: >> Build a latest kernel with 64r6el_defconfig (tested on 6.6, >> next-20240506). >> >> Then run: >> ``` >> qemu-system-mips64el -M boston -cpu I6500 -kernel ~/linux-next/vmlinux >> -smp 4,cores=2,threads=2 -append "console=ttyS0,115200" -nographic >> ``` >> In dmesg of guest kernel: >> ``` >> [ 0.000000] VP topology {2,2} total 4 >> ... >> [ 0.085190] smp: Bringing up secondary CPUs ... >> [ 0.090219] Primary instruction cache 64kB, VIPT, 4-way, linesize 64 >> bytes. >> [ 0.095461] Primary data cache 64kB, 4-way, PIPT, no aliases, >> linesize 64 bytes >> [ 0.096658] CPU1 revision is: 0001b000 (MIPS I6500) >> [ 0.096718] FPU revision is: 20f30300 >> [ 0.124711] Synchronize counters for CPU 1: done. >> [ 0.940979] Primary instruction cache 64kB, VIPT, 4-way, linesize 64 >> bytes. >> [ 0.941041] Primary data cache 64kB, 4-way, PIPT, no aliases, >> linesize 64 bytes >> [ 0.941256] CPU2 revision is: 0001b000 (MIPS I6500) >> [ 0.941289] FPU revision is: 20f30300 >> [ 0.965322] Synchronize counters for CPU 2: done. >> [ 1.260937] Primary instruction cache 64kB, VIPT, 4-way, linesize 64 >> bytes. >> [ 1.261001] Primary data cache 64kB, 4-way, PIPT, no aliases, >> linesize 64 bytes >> [ 1.261172] CPU3 revision is: 0001b000 (MIPS I6500) >> [ 1.261209] FPU revision is: 20f30300 >> [ 1.285390] Synchronize counters for CPU 3: done. >> [ 1.346985] smp: Brought up 1 node, 4 CPUs >> ``` >> >> Please review. >> >> Thanks >> >> To: qemu-devel@nongnu.org >> Cc: Philippe Mathieu-Daudé >> >> Signed-off-by: Jiaxun Yang >> --- >> Jiaxun Yang (5): >> target/mips: Make globalnumber a CPU property >> hw/msic/mips_cmgcr: Implement multicore functions >> hw/msic/mips_cpc: Implement multi core support >> hw/mips/cps: Implement multi core support >> hw/mips/boston: Implement multi core support >> >> hw/mips/boston.c | 37 +++++++++- >> hw/mips/cps.c | 66 ++++++++++------- >> hw/misc/mips_cmgcr.c | 168 +++++++++++++++++++++++++++++++++++-------- >> hw/misc/mips_cpc.c | 97 ++++++++++++++++++------- >> include/hw/mips/cps.h | 1 + >> include/hw/misc/mips_cmgcr.h | 87 +++++++++++++++++++--- >> include/hw/misc/mips_cpc.h | 15 +++- >> target/mips/cpu.c | 16 ++++- >> target/mips/cpu.h | 10 ++- >> target/mips/sysemu/machine.c | 5 +- >> 10 files changed, 403 insertions(+), 99 deletions(-) >> --- >> base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 >> change-id: 20240506-mips-smp-9af9e71ad8c2 >> >> Best regards, >> -- >> Jiaxun Yang >