From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Weiser <michael.weiser@gmx.de>, qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be
Date: Mon, 1 Jan 2018 15:06:21 -0800 [thread overview]
Message-ID: <19080078-e96a-cc33-bb02-97f9b726d080@linaro.org> (raw)
In-Reply-To: <20171230225622.97409-1-michael.weiser@gmx.de>
On 12/30/2017 02:56 PM, Michael Weiser wrote:
> ldxp loads two consecutive doublewords from memory regardless of CPU
> endianness. On store, stlxp currently assumes to work with a 128bit
> value and consequently switches order in big-endian mode. With this
> change it packs the doublewords in reverse order in anticipation of the
> 128bit big-endian store operation interposing them so they end up in
> memory in the right order. This makes it work for both MTTCG and !MTTCG.
> It effectively implements the ARM ARM STLXP operation pseudo-code:
>
> data = if BigEndian() then el1:el2 else el2:el1;
>
> With this change an aarch64_be Linux 4.14.4 kernel succeeds to boot up
> in system emulation mode.
>
> Signed-off-by: Michael Weiser <michael.weiser@gmx.de>
> ---
> target/arm/helper-a64.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> v2:
> - make it work for MTTCG as well by catering to the 128bit expectation
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> + * 128bit store but two doulbewords stored consecutively */
^^ typo
r~
next prev parent reply other threads:[~2018-01-01 23:06 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-30 22:56 [Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be Michael Weiser
2018-01-01 23:06 ` Richard Henderson [this message]
2018-01-02 19:02 ` Michael Weiser
2018-01-08 12:09 ` Peter Maydell
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