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From: Joao Martins <joao.m.martins@oracle.com>
To: qemu-devel@nongnu.org, Igor Mammedov <imammedo@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Daniel Jordan <daniel.m.jordan@oracle.com>,
	David Edmondson <david.edmondson@oracle.com>,
	Alex Williamson <alex.williamson@redhat.com>,
	Ani Sinha <ani@anisinha.ca>, Paolo Bonzini <pbonzini@redhat.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH v3 5/6] i386/pc: warn if phys-bits is too low
Date: Thu, 24 Feb 2022 14:42:37 +0000	[thread overview]
Message-ID: <191acc21-c6de-1da8-feeb-b1f85ef92ef1@oracle.com> (raw)
In-Reply-To: <20220223184455.9057-6-joao.m.martins@oracle.com>

On 2/23/22 18:44, Joao Martins wrote:
> @@ -896,6 +897,15 @@ void pc_memory_init(PCMachineState *pcms,
>  
>      x86_update_above_4g_mem_start(pcms, pci_hole64_size);
>  
> +    maxphysaddr = ((hwaddr)1 << X86_CPU(first_cpu)->phys_bits) - 1;
> +    maxusedaddr = x86_max_phys_addr(pcms, pci_hole64_size);
> +    if (maxphysaddr < maxusedaddr) {
> +        warn_report("Address space above 4G at %"PRIx64"-%"PRIx64
> +                    " phys-bits too low (%u)",
> +                    x86ms->above_4g_mem_start, maxusedaddr,
> +                    X86_CPU(first_cpu)->phys_bits);
> +    }
> +
And in addition to the change in patch 4, for 32-bit I will change this
to an error_report(...) and exit right after, and updating commit message
accordingly. The error message changes slightly too given that it was
too specific to the above 4G region. All qtests pass.

diffstat below:

@@ -904,6 +905,16 @@ void pc_memory_init(PCMachineState *pcms,

     x86_update_above_4g_mem_start(pcms, pci_hole64_size);

+    maxphysaddr = ((hwaddr)1 << X86_CPU(first_cpu)->phys_bits) - 1;
+    maxusedaddr = x86_max_phys_addr(pcms, pci_hole64_size);
+    if (maxphysaddr < maxusedaddr) {
+        error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
+                     " phys-bits too low (%u)",
+                     maxphysaddr, maxusedaddr,
+                     X86_CPU(first_cpu)->phys_bits);
+        exit(EXIT_FAILURE);
+    }


  reply	other threads:[~2022-02-24 14:47 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-23 18:44 [PATCH v3 0/6] i386/pc: Fix creation of >= 1010G guests on AMD systems with IOMMU Joao Martins
2022-02-23 18:44 ` [PATCH v3 1/6] hw/i386: add 4g boundary start to X86MachineState Joao Martins
2022-02-23 18:44 ` [PATCH v3 2/6] i386/pc: create pci-host qdev prior to pc_memory_init() Joao Martins
2022-02-23 18:44 ` [PATCH v3 3/6] i386/pc: pass pci_hole64_size " Joao Martins
2022-02-23 18:44 ` [PATCH v3 4/6] i386/pc: relocate 4g start to 1T where applicable Joao Martins
2022-02-23 21:22   ` Michael S. Tsirkin
2022-02-23 23:35     ` Joao Martins
2022-02-24 16:07       ` Joao Martins
2022-02-24 17:23         ` Michael S. Tsirkin
2022-02-24 17:54           ` Joao Martins
2022-02-24 18:30             ` Michael S. Tsirkin
2022-02-24 19:44               ` Joao Martins
2022-02-24 19:54                 ` Michael S. Tsirkin
2022-02-24 20:04                   ` Joao Martins
2022-02-24 20:12                     ` Michael S. Tsirkin
2022-02-24 20:34                       ` Joao Martins
2022-02-24 21:40                         ` Alex Williamson
2022-02-25 12:36                           ` Joao Martins
2022-02-25 12:49                             ` Michael S. Tsirkin
2022-02-25 17:40                               ` Joao Martins
2022-02-25 16:15                             ` Alex Williamson
2022-02-25 17:40                               ` Joao Martins
2022-02-25  5:22                         ` Michael S. Tsirkin
2022-02-25 12:36                           ` Joao Martins
2022-02-25  3:52               ` Jason Wang
2022-02-24 14:27   ` Joao Martins
2022-02-23 18:44 ` [PATCH v3 5/6] i386/pc: warn if phys-bits is too low Joao Martins
2022-02-24 14:42   ` Joao Martins [this message]
2022-02-23 18:44 ` [PATCH v3 6/6] i386/pc: restrict AMD only enforcing of valid IOVAs to new machine type Joao Martins

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