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Thu, 8 Feb 2024 11:34:53 +0100 (CET) Date: Thu, 8 Feb 2024 11:34:53 +0100 (CET) From: =?utf-8?B?SW7DqHM=?= Varhol To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Arnaud Minier , qemu-devel@nongnu.org, Paolo Bonzini , Peter Maydell , Thomas Huth , Laurent Vivier , qemu-arm@nongnu.org, Samuel Tardieu , Alistair Francis , Alistair Francis Message-ID: <1921238046.591194.1707388492770.JavaMail.zimbra@enst.fr> In-Reply-To: <5a7594d9-3fbd-4d90-a5f9-81b7b845fba7@linaro.org> References: <20240109160658.311932-1-ines.varhol@telecom-paris.fr> <20240109160658.311932-3-ines.varhol@telecom-paris.fr> <5a7594d9-3fbd-4d90-a5f9-81b7b845fba7@linaro.org> Subject: Re: [PATCH v8 2/3] hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="=_0c589f4e-91b5-4b54-be9b-d5d761903ff9" X-Originating-IP: [::ffff:80.125.0.74] X-Mailer: Zimbra 9.0.0_GA_4583 (ZimbraModernWebClient - FF122 (Linux)/9.0.0_GA_4583) Thread-Topic: hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC Thread-Index: IOgIHmd0TWUC9N/BQ6cWQF1+AdeUCA== Received-SPF: pass client-ip=137.194.2.222; envelope-from=ivarhol-21@enst.fr; helo=zproxy3.enst.fr X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --=_0c589f4e-91b5-4b54-be9b-d5d761903ff9 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =20 =20 Hi, =20 > De: Philippe =20 > Envoy=C3=A9: mercredi 7 f=C3=A9vrier 2024 23:02 CET=20 >=C2=A0=20 > Hi In=C3=A8s,=20 >=C2=A0=20 > (this is now commit 52671f69f7).=20 >=C2=A0=20 > On 9/1/24 17:06, In=C3=A8s Varhol wrote:=20 > > Tested-by: Philippe Mathieu-Daud=C3=A9 =20 > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 =20 > > Reviewed-by: Alistair Francis =20 > > Signed-off-by: Arnaud Minier =20 > > Signed-off-by: In=C3=A8s Varhol =20 > > ---=20 > > hw/arm/Kconfig | 1 +=20 > > hw/arm/stm32l4x5_soc.c | 52 +++++++++++++++++++++++++++++++++-=20 > > include/hw/arm/stm32l4x5_soc.h | 3 ++=20 > > 3 files changed, 55 insertions(+), 1 deletion(-)=20 >=C2=A0=20 >=C2=A0=20 > > +#define NUM_EXTI_IRQ 40=20 > > +/* Match exti line connections with their CPU IRQ number */=20 > > +/* See Vector Table (Reference Manual p.396) */=20 > > +static const int exti_irq[NUM_EXTI_IRQ] =3D {=20 > > + 6, /* GPIO[0] */=20 > > + 7, /* GPIO[1] */=20 > > + 8, /* GPIO[2] */=20 > > + 9, /* GPIO[3] */=20 > > + 10, /* GPIO[4] */=20 > > + 23, 23, 23, 23, 23, /* GPIO[5..9] */=20 > > + 40, 40, 40, 40, 40, 40, /* GPIO[10..15] */=20 >=C2=A0=20 > I'm sorry because I missed that earlier, and I'm surprised=20 > you aren't chasing weird bugs. Due to how QEMU IRQs are=20 > implemented, we can not wire multiple input lines to the same=20 > output without using an intermediate "OR gate". We model it=20 > as TYPE_OR_IRQ. See the comment in "hw/qdev-core.h" added in=20 > commit cd07d7f9f5 ("qdev: Document GPIO related functions"):=20 =C2=A0=20 Better fixing it now than later :) I must admit I didn't pay attention to the particularity of EXTI5 to 15.=20 Current exti tests don't even use these lines, a testcase will have=20 to be added. Otherwise we mostly ran executables using GPIOs as output,=20 so no weird bugs encountered.=20 =C2=A0=20 Thank you for noticing !=20 Ines=20 =C2=A0=20 >=C2=A0=20 > * It is not valid to try to connect one outbound GPIO to multiple=20 > * qemu_irqs at once, or to connect multiple outbound GPIOs to the=20 > * same qemu_irq. (Warning: there is no assertion or other guard to=20 > * catch this error: the model will just not do the right thing.)=20 > * Instead, for fan-out you can use the TYPE_SPLIT_IRQ device: connect=20 > * a device's outbound GPIO to the splitter's input, and connect each=20 > * of the splitter's outputs to a different device. For fan-in you=20 > * can use the TYPE_OR_IRQ device, which is a model of a logical OR=20 > * gate with multiple inputs and one output.=20 >=C2=A0=20 > So for example for the GPIO[10..15] you need to create a 6-line=20 > OR gate as (totally untested):=20 >=C2=A0=20 > /* 6-line OR IRQ gate */=20 > Object *orgate40 =3D object_new(TYPE_OR_IRQ);=20 > object_property_set_int(orgate40, "num-lines", 6, &error_fatal);=20 > qdev_realize(DEVICE(orgate), NULL, &error_fatal);=20 >=C2=A0=20 > /* OR gate -> IRQ #40 */=20 > qdev_connect_gpio_out(DEVICE(orgate40), 0,=20 > qdev_get_gpio_in(armv7m, 40));=20 >=C2=A0=20 > /* EXTI GPIO[10..15] -> OR gate */=20 > for (unsigned i =3D 0; i < 6; i++) {=20 > sysbus_connect_irq(SYS_BUS_DEVICE(&s->exti), 10 + i,=20 > qdev_get_gpio_in(DEVICE(orgate40), i));=20 > }=20 >=C2=A0=20 > > + 1, /* PVD */=20 > > + 67, /* OTG_FS_WKUP, Direct */=20 > > + 41, /* RTC_ALARM */=20 > > + 2, /* RTC_TAMP_STAMP2/CSS_LSE */=20 > > + 3, /* RTC wakeup timer */=20 > > + 63, /* COMP1 */=20 > > + 63, /* COMP2 */=20 > > + 31, /* I2C1 wakeup, Direct */=20 > > + 33, /* I2C2 wakeup, Direct */=20 > > + 72, /* I2C3 wakeup, Direct */=20 > > + 37, /* USART1 wakeup, Direct */=20 > > + 38, /* USART2 wakeup, Direct */=20 > > + 39, /* USART3 wakeup, Direct */=20 > > + 52, /* UART4 wakeup, Direct */=20 > > + 53, /* UART4 wakeup, Direct */=20 > > + 70, /* LPUART1 wakeup, Direct */=20 > > + 65, /* LPTIM1, Direct */=20 > > + 66, /* LPTIM2, Direct */=20 > > + 76, /* SWPMI1 wakeup, Direct */=20 > > + 1, /* PVM1 wakeup */=20 > > + 1, /* PVM2 wakeup */=20 > > + 1, /* PVM3 wakeup */=20 > > + 1, /* PVM4 wakeup */=20 > > + 78 /* LCD wakeup, Direct */=20 > > +};=20 >=C2=A0=20 > > + busdev =3D SYS_BUS_DEVICE(&s->exti);=20 > > + if (!sysbus_realize(busdev, errp)) {=20 > > + return;=20 > > + }=20 > > + sysbus_mmio_map(busdev, 0, EXTI_ADDR);=20 > > + for (unsigned i =3D 0; i < NUM_EXTI_IRQ; i++) {=20 > > + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));= =20 >=C2=A0=20 > ^^^^^^^^^^=20 > > + }=20 > Regards,=20 >=C2=A0=20 > Phil.=C2=A0 =20 --=_0c589f4e-91b5-4b54-be9b-d5d761903ff9 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable
Hi,

> De: Philippe <philmd@linaro.org>
> Envoy=C3=A9: mercredi 7 f=C3=A9vrier 2024 23:02 CET
> 
> Hi In=C3=A8s,
> 
> (this is now commit 52671f69f7).
> 
> On 9/1/24 17:06, In=C3=A8s Varhol wrote:
> > Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org= >
> > Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.o= rg>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com&g= t;
> > Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris= .fr>
> > Signed-off-by: In=C3=A8s Varhol <ines.varhol@telecom-pari= s.fr>
> > ---
> > hw/arm/Kconfig | 1 +
> > hw/arm/stm32l4x5_soc.c | 52 ++++++++++++++++++++++++++++++++= +-
> > include/hw/arm/stm32l4x5_soc.h | 3 ++
> > 3 files changed, 55 insertions(+), 1 deletion(-)
> 
> 
> > +#define NUM_EXTI_IRQ 40
> > +/* Match exti line connections with their CPU IRQ number */=
> > +/* See Vector Table (Reference Manual p.396) */
> > +static const int exti_irq[NUM_EXTI_IRQ] =3D {
> > + 6, /* GPIO[0] */
> > + 7, /* GPIO[1] */
> > + 8, /* GPIO[2] */
> > + 9, /* GPIO[3] */
> > + 10, /* GPIO[4] */
> > + 23, 23, 23, 23, 23, /* GPIO[5..9] */
> > + 40, 40, 40, 40, 40, 40, /* GPIO[10..15] */
> 
> I'm sorry because I missed that earlier, and I'm surprised
> you aren't chasing weird bugs. Due to how QEMU IRQs are
> implemented, we can not wire multiple input lines to the same
> output without using an intermediate "OR gate". We model it
> as TYPE_OR_IRQ. See the comment in "hw/qdev-core.h" added in
> commit cd07d7f9f5 ("qdev: Document GPIO related functions"):
 
Better fixing it now than later :)
I must admit I didn't pay attent= ion to the particularity of EXTI5 to 15.
Current exti tests don't even use these lines, a testcase will have
to be added. Otherwise we mostly ran executables using GPIOs as output= ,
so no weird bugs encountered.
 
Thank you for noticing !
Ines
 
> 
> * It is not valid to try to connect one outbound GPIO to multiple=
> * qemu_irqs at once, or to connect multiple outbound GPIOs to the=
> * same qemu_irq. (Warning: there is no assertion or other guard t= o
> * catch this error: the model will just not do the right thing.)<= /div>
> * Instead, for fan-out you can use the TYPE_SPLIT_IRQ device: con= nect
> * a device's outbound GPIO to the splitter's input, and connect e= ach
> * of the splitter's outputs to a different device. For fan-in you=
> * can use the TYPE_OR_IRQ device, which is a model of a logical O= R
> * gate with multiple inputs and one output.
> 
> So for example for the GPIO[10..15] you need to create a 6-line
> OR gate as (totally untested):
> 
> /* 6-line OR IRQ gate */
> Object *orgate40 =3D object_new(TYPE_OR_IRQ);
> object_property_set_int(orgate40, "num-lines", 6, &error_fata= l);
> qdev_realize(DEVICE(orgate), NULL, &error_fatal);
> 
> /* OR gate -> IRQ #40 */
> qdev_connect_gpio_out(DEVICE(orgate40), 0,
> qdev_get_gpio_in(armv7m, 40));
> 
> /* EXTI GPIO[10..15] -> OR gate */
> for (unsigned i =3D 0; i < 6; i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->exti), 10 + i,
> qdev_get_gpio_in(DEVICE(orgate40), i));
> }
> 
> > + 1, /* PVD */
> > + 67, /* OTG_FS_WKUP, Direct */
> > + 41, /* RTC_ALARM */
> > + 2, /* RTC_TAMP_STAMP2/CSS_LSE */
> > + 3, /* RTC wakeup timer */
> > + 63, /* COMP1 */
> > + 63, /* COMP2 */
> > + 31, /* I2C1 wakeup, Direct */
> > + 33, /* I2C2 wakeup, Direct */
> > + 72, /* I2C3 wakeup, Direct */
> > + 37, /* USART1 wakeup, Direct */
> > + 38, /* USART2 wakeup, Direct */
> > + 39, /* USART3 wakeup, Direct */
> > + 52, /* UART4 wakeup, Direct */
> > + 53, /* UART4 wakeup, Direct */
> > + 70, /* LPUART1 wakeup, Direct */
> > + 65, /* LPTIM1, Direct */
> > + 66, /* LPTIM2, Direct */
> > + 76, /* SWPMI1 wakeup, Direct */
> > + 1, /* PVM1 wakeup */
> > + 1, /* PVM2 wakeup */
> > + 1, /* PVM3 wakeup */
> > + 1, /* PVM4 wakeup */
> > + 78 /* LCD wakeup, Direct */
> > +};
> 
> > + busdev =3D SYS_BUS_DEVICE(&s->exti);
> > + if (!sysbus_realize(busdev, errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(busdev, 0, EXTI_ADDR);
> > + for (unsigned i =3D 0; i < NUM_EXTI_IRQ; i++) {
> > + sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, ext= i_irq[i]));
> 
> ^^^^^^^^^^
> > + }
> Regards,
> 
> Phil. 
--=_0c589f4e-91b5-4b54-be9b-d5d761903ff9--