From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Bin Meng <bmeng.cn@gmail.com>, qemu-devel@nongnu.org
Cc: Bin Meng <bmeng@tinylab.org>, Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH v2 18/18] target/riscv: Group all predicate() routines together
Date: Thu, 2 Mar 2023 10:47:21 +0800 [thread overview]
Message-ID: <1928ebe9-a2fb-c014-a7b7-632c5c56dfd0@linux.alibaba.com> (raw)
In-Reply-To: <20230228104035.1879882-19-bmeng@tinylab.org>
On 2023/2/28 21:45, Bin Meng wrote:
> From: Bin Meng <bmeng@tinylab.org>
>
> Move sstc()/sstc32() to where all predicate() routines live, and
> smstateen_acc_ok() to near {read,write}_xenvcfg().
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> ---
>
> Changes in v2:
> - move smstateen_acc_ok() to near {read,write}_xenvcfg()
>
> target/riscv/csr.c | 177 ++++++++++++++++++++++-----------------------
> 1 file changed, 87 insertions(+), 90 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 785f6f4d45..3a7e0217e2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -40,42 +40,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
> csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
> }
>
> -/* Predicates */
Don't remove this comment. Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> -#if !defined(CONFIG_USER_ONLY)
> -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
> - uint64_t bit)
> -{
> - bool virt = riscv_cpu_virt_enabled(env);
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - if (!(env->mstateen[index] & bit)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - if (virt) {
> - if (!(env->hstateen[index] & bit)) {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> -
> - if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> - }
> -
> - if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
> - if (!(env->sstateen[index] & bit)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> - }
> -
> - return RISCV_EXCP_NONE;
> -}
> -#endif
> -
> static RISCVException fs(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -399,6 +363,60 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException sstc(CPURISCVState *env, int csrno)
> +{
> + RISCVCPU *cpu = env_archcpu(env);
> + bool hmode_check = false;
> +
> + if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
> + hmode_check = true;
> + }
> +
> + RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + if (env->debugger) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + if (env->priv == PRV_M) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + /*
> + * No need of separate function for rv32 as menvcfg stores both menvcfg
> + * menvcfgh for RV32.
> + */
> + if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
> + get_field(env->menvcfg, MENVCFG_STCE))) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + if (riscv_cpu_virt_enabled(env)) {
> + if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->henvcfg, HENVCFG_STCE))) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException sstc_32(CPURISCVState *env, int csrno)
> +{
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return sstc(env, csrno);
> +}
> +
> /* Checks if PointerMasking registers could be accessed */
> static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> {
> @@ -943,60 +961,6 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException sstc(CPURISCVState *env, int csrno)
> -{
> - RISCVCPU *cpu = env_archcpu(env);
> - bool hmode_check = false;
> -
> - if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
> - hmode_check = true;
> - }
> -
> - RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
> - if (ret != RISCV_EXCP_NONE) {
> - return ret;
> - }
> -
> - if (env->debugger) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - if (env->priv == PRV_M) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - /*
> - * No need of separate function for rv32 as menvcfg stores both menvcfg
> - * menvcfgh for RV32.
> - */
> - if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
> - get_field(env->menvcfg, MENVCFG_STCE))) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - if (riscv_cpu_virt_enabled(env)) {
> - if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
> - get_field(env->henvcfg, HENVCFG_STCE))) {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> - }
> -
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException sstc_32(CPURISCVState *env, int csrno)
> -{
> - if (riscv_cpu_mxl(env) != MXL_RV32) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - return sstc(env, csrno);
> -}
> -
> static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -1944,6 +1908,39 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
> + uint64_t bit)
> +{
> + bool virt = riscv_cpu_virt_enabled(env);
> + RISCVCPU *cpu = env_archcpu(env);
> +
> + if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + if (!(env->mstateen[index] & bit)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + if (virt) {
> + if (!(env->hstateen[index] & bit)) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> +
> + if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> + }
> +
> + if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
> + if (!(env->sstateen[index] & bit)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
prev parent reply other threads:[~2023-03-02 2:48 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-28 10:40 ` [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
2023-02-28 12:07 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
2023-02-28 12:08 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
2023-02-28 10:40 ` [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-03-01 9:52 ` LIU Zhiwei
2023-03-01 9:55 ` Bin Meng
2023-03-01 23:43 ` Palmer Dabbelt
2023-03-02 0:30 ` Bin Meng
2023-03-02 0:58 ` Palmer Dabbelt
2023-03-02 2:43 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-28 10:40 ` [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-28 10:40 ` [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-28 10:40 ` [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-28 10:40 ` [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-28 10:40 ` [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-28 13:45 ` [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-28 13:45 ` [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-28 13:45 ` [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-28 13:45 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-03-02 2:44 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
2023-03-02 2:44 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-03-02 2:45 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 18/18] target/riscv: Group all predicate() routines together Bin Meng
2023-03-02 2:47 ` LIU Zhiwei [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1928ebe9-a2fb-c014-a7b7-632c5c56dfd0@linux.alibaba.com \
--to=zhiwei_liu@linux.alibaba.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=bmeng.cn@gmail.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).