* [Qemu-devel] [PATCH 0/4] target/mips: Misc fixes and maintenance for 4.1
@ 2019-06-20 9:19 Aleksandar Markovic
2019-06-20 9:19 ` [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board Aleksandar Markovic
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Aleksandar Markovic @ 2019-06-20 9:19 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo, amarkovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
This series contains miscelaneous fixes, improvements, and
maintainance items intended to be integrated into QEMU 4.1.
I will gradually add patches by the end of June 2019.
v1->v2:
- added two patches on cleaning checkpatch warnings
Aleksandar Markovic (4):
MAINTAINERS: Update file items for MIPS Malta board
MAINTAINERS: Consolidate MIPS disassembler-related items
target/mips: Fix some space checkpatch errors in translate.c
target/mips: Fix if-else arms checkpatch errors in translate.c
MAINTAINERS | 6 +-
target/mips/translate.c | 232 +++++++++++++++++++++++++++---------------------
2 files changed, 133 insertions(+), 105 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread* [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board 2019-06-20 9:19 [Qemu-devel] [PATCH 0/4] target/mips: Misc fixes and maintenance for 4.1 Aleksandar Markovic @ 2019-06-20 9:19 ` Aleksandar Markovic 2019-06-20 11:13 ` Philippe Mathieu-Daudé 2019-06-20 9:19 ` [Qemu-devel] [PATCH 2/4] MAINTAINERS: Consolidate MIPS disassembler-related items Aleksandar Markovic ` (2 subsequent siblings) 3 siblings, 1 reply; 8+ messages in thread From: Aleksandar Markovic @ 2019-06-20 9:19 UTC (permalink / raw) To: qemu-devel; +Cc: arikalo, amarkovic From: Aleksandar Markovic <amarkovic@wavecomp.com> hw/mips/gt64xxx_pci.c is used for Malta only, so it is logical to place this file in Malta board section of the MAINTAINERS file. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index acbad13..869e87b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -930,6 +930,7 @@ M: Aurelien Jarno <aurelien@aurel32.net> R: Aleksandar Rikalo <arikalo@wavecomp.com> S: Maintained F: hw/mips/mips_malta.c +F: hw/mips/gt64xxx_pci.c F: tests/acceptance/linux_ssh_mips_malta.py Mipssim -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board 2019-06-20 9:19 ` [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board Aleksandar Markovic @ 2019-06-20 11:13 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2019-06-20 11:13 UTC (permalink / raw) To: Aleksandar Markovic, qemu-devel; +Cc: arikalo, amarkovic On 6/20/19 11:19 AM, Aleksandar Markovic wrote: > From: Aleksandar Markovic <amarkovic@wavecomp.com> > > hw/mips/gt64xxx_pci.c is used for Malta only, so it is logical to > place this file in Malta board section of the MAINTAINERS file. > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index acbad13..869e87b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -930,6 +930,7 @@ M: Aurelien Jarno <aurelien@aurel32.net> > R: Aleksandar Rikalo <arikalo@wavecomp.com> > S: Maintained > F: hw/mips/mips_malta.c > +F: hw/mips/gt64xxx_pci.c > F: tests/acceptance/linux_ssh_mips_malta.py > > Mipssim > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 2/4] MAINTAINERS: Consolidate MIPS disassembler-related items 2019-06-20 9:19 [Qemu-devel] [PATCH 0/4] target/mips: Misc fixes and maintenance for 4.1 Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board Aleksandar Markovic @ 2019-06-20 9:19 ` Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 3/4] target/mips: Fix some space checkpatch errors in translate.c Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms " Aleksandar Markovic 3 siblings, 0 replies; 8+ messages in thread From: Aleksandar Markovic @ 2019-06-20 9:19 UTC (permalink / raw) To: qemu-devel; +Cc: arikalo, amarkovic From: Aleksandar Markovic <amarkovic@wavecomp.com> Eliminate duplicate MIPS disassembler-related items in the MAINTAINERS file, and use wildcards to shorten the list of involved files. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> --- MAINTAINERS | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 869e87b..f9f66e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -212,9 +212,7 @@ R: Aleksandar Rikalo <arikalo@wavecomp.com> S: Maintained F: target/mips/ F: default-configs/*mips* -F: disas/mips.c -F: disas/nanomips.cpp -F: disas/nanomips.h +F: disas/*mips* F: hw/intc/mips_gic.c F: hw/mips/ F: hw/misc/mips_* @@ -2321,7 +2319,6 @@ M: Aurelien Jarno <aurelien@aurel32.net> R: Aleksandar Rikalo <arikalo@wavecomp.com> S: Maintained F: tcg/mips/ -F: disas/mips.c PPC TCG target M: Richard Henderson <rth@twiddle.net> -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 3/4] target/mips: Fix some space checkpatch errors in translate.c 2019-06-20 9:19 [Qemu-devel] [PATCH 0/4] target/mips: Misc fixes and maintenance for 4.1 Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 2/4] MAINTAINERS: Consolidate MIPS disassembler-related items Aleksandar Markovic @ 2019-06-20 9:19 ` Aleksandar Markovic 2019-06-20 11:11 ` Philippe Mathieu-Daudé 2019-06-20 9:19 ` [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms " Aleksandar Markovic 3 siblings, 1 reply; 8+ messages in thread From: Aleksandar Markovic @ 2019-06-20 9:19 UTC (permalink / raw) To: qemu-devel; +Cc: arikalo, amarkovic From: Aleksandar Markovic <amarkovic@wavecomp.com> Remove some space-related checkpatch warning. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> --- target/mips/translate.c | 126 +++++++++++++++++++++++++----------------------- 1 file changed, 65 insertions(+), 61 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index a3cf976..324b32a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2617,7 +2617,7 @@ static const char * const mxuregnames[] = { } while (0) /* General purpose registers moves. */ -static inline void gen_load_gpr (TCGv t, int reg) +static inline void gen_load_gpr(TCGv t, int reg) { if (reg == 0) tcg_gen_movi_tl(t, 0); @@ -2625,14 +2625,14 @@ static inline void gen_load_gpr (TCGv t, int reg) tcg_gen_mov_tl(t, cpu_gpr[reg]); } -static inline void gen_store_gpr (TCGv t, int reg) +static inline void gen_store_gpr(TCGv t, int reg) { if (reg != 0) tcg_gen_mov_tl(cpu_gpr[reg], t); } /* Moves to/from shadow registers. */ -static inline void gen_load_srsgpr (int from, int to) +static inline void gen_load_srsgpr(int from, int to) { TCGv t0 = tcg_temp_new(); @@ -2839,7 +2839,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) } } -static inline int get_fp_bit (int cc) +static inline int get_fp_bit(int cc) { if (cc) return 24 + cc; @@ -2848,7 +2848,8 @@ static inline int get_fp_bit (int cc) } /* Addresses computation */ -static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) +static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, + TCGv arg1) { tcg_gen_add_tl(ret, arg0, arg1); @@ -3328,8 +3329,8 @@ OP_LD_ATOMIC(lld,ld64); #endif #undef OP_LD_ATOMIC -static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, - int base, int offset) +static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, + int base, int offset) { if (base == 0) { tcg_gen_movi_tl(addr, offset); @@ -3341,7 +3342,7 @@ static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, } } -static target_ulong pc_relative_pc (DisasContext *ctx) +static target_ulong pc_relative_pc(DisasContext *ctx) { target_ulong pc = ctx->base.pc_next; @@ -3578,8 +3579,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, } /* Store */ -static void gen_st (DisasContext *ctx, uint32_t opc, int rt, - int base, int offset) +static void gen_st(DisasContext *ctx, uint32_t opc, int rt, + int base, int offset) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -3717,8 +3718,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, } /* Load and store */ -static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, - TCGv t0) +static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, + TCGv t0) { /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -5132,8 +5133,8 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } -static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) +static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -5196,8 +5197,8 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } -static void gen_cl (DisasContext *ctx, uint32_t opc, - int rd, int rs) +static void gen_cl(DisasContext *ctx, uint32_t opc, + int rd, int rs) { TCGv t0; @@ -6188,8 +6189,8 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, /* special3 bitfield operations */ -static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, - int rs, int lsb, int msb) +static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, + int rs, int lsb, int msb) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -6259,7 +6260,7 @@ fail: tcg_temp_free(t1); } -static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) +static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) { TCGv t0; @@ -6502,7 +6503,7 @@ static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) tcg_temp_free_i64(t0); } -static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) +static inline void gen_mfc0_load32(TCGv arg, target_ulong off) { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -6511,13 +6512,13 @@ static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) tcg_temp_free_i32(t0); } -static inline void gen_mfc0_load64 (TCGv arg, target_ulong off) +static inline void gen_mfc0_load64(TCGv arg, target_ulong off) { tcg_gen_ld_tl(arg, cpu_env, off); tcg_gen_ext32s_tl(arg, arg); } -static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) +static inline void gen_mtc0_store32(TCGv arg, target_ulong off) { TCGv_i32 t0 = tcg_temp_new_i32(); @@ -10077,7 +10078,8 @@ die: generate_exception_end(ctx, EXCP_RI); } -static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) +static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rt, int rd) { const char *opn = "ldst"; @@ -10633,7 +10635,8 @@ enum r6_f_cmp_op { R6_OPC_CMP_SUNE_D = FOP(26, FMT_L), R6_OPC_CMP_SNE_D = FOP(27, FMT_L), }; -static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) + +static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) { TCGv t0 = tcg_temp_new(); @@ -10714,7 +10717,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) tcg_temp_free(t0); } -static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) +static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) { TCGLabel *l1; TCGCond cond; @@ -10763,7 +10766,8 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, tcg_temp_free_i32(t0); } -static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) +static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, + int tf) { int cond; TCGv_i32 t0 = tcg_temp_new_i32(); @@ -10886,8 +10890,8 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, tcg_temp_free_i64(t1); } -static void gen_farith (DisasContext *ctx, enum fopcode op1, - int ft, int fs, int fd, int cc) +static void gen_farith(DisasContext *ctx, enum fopcode op1, + int ft, int fs, int fd, int cc) { uint32_t func = ctx->opcode & 0x3f; switch (op1) { @@ -12314,8 +12318,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, } /* Coprocessor 3 (FPU) */ -static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, - int fd, int fs, int base, int index) +static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, + int fd, int fs, int base, int index) { TCGv t0 = tcg_temp_new(); @@ -12394,8 +12398,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); } -static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, - int fd, int fr, int fs, int ft) +static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, + int fd, int fr, int fs, int ft) { switch (opc) { case OPC_ALNV_PS: @@ -13157,17 +13161,17 @@ enum { RR_RY_CNVT_SEW = 0x6, }; -static int xlat (int r) +static int xlat(int r) { static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; return map[r]; } -static void gen_mips16_save (DisasContext *ctx, - int xsregs, int aregs, - int do_ra, int do_s0, int do_s1, - int framesize) +static void gen_mips16_save(DisasContext *ctx, + int xsregs, int aregs, + int do_ra, int do_s0, int do_s1, + int framesize) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -13322,10 +13326,10 @@ static void gen_mips16_save (DisasContext *ctx, tcg_temp_free(t2); } -static void gen_mips16_restore (DisasContext *ctx, - int xsregs, int aregs, - int do_ra, int do_s0, int do_s1, - int framesize) +static void gen_mips16_restore(DisasContext *ctx, + int xsregs, int aregs, + int do_ra, int do_s0, int do_s1, + int framesize) { int astatic; TCGv t0 = tcg_temp_new(); @@ -13428,8 +13432,8 @@ static void gen_mips16_restore (DisasContext *ctx, tcg_temp_free(t2); } -static void gen_addiupc (DisasContext *ctx, int rx, int imm, - int is_64_bit, int extended) +static void gen_addiupc(DisasContext *ctx, int rx, int imm, + int is_64_bit, int extended) { TCGv t0; @@ -13459,9 +13463,9 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, } #if defined(TARGET_MIPS64) -static void decode_i64_mips16 (DisasContext *ctx, - int ry, int funct, int16_t offset, - int extended) +static void decode_i64_mips16(DisasContext *ctx, + int ry, int funct, int16_t offset, + int extended) { switch (funct) { case I64_LDSP: @@ -13520,7 +13524,7 @@ static void decode_i64_mips16 (DisasContext *ctx, } #endif -static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) +static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { int extend = cpu_lduw_code(env, ctx->base.pc_next + 2); int op, rx, ry, funct, sa; @@ -13734,7 +13738,7 @@ static inline void gen_helper_do_semihosting(void *env) } #endif -static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) +static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) { int rx, ry; int sa; @@ -13957,7 +13961,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) case M16_OPC_LWPC: gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case M16_OPC_LWU: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14061,7 +14065,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) case RR_SRAV: gen_shift(ctx, OPC_SRAV, ry, rx, ry); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case RR_DSRL: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14124,7 +14128,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) case RR_MFLO: gen_HILO(ctx, OPC_MFLO, 0, rx); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case RR_DSRA: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14158,7 +14162,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) case RR_DIVU: gen_muldiv(ctx, OPC_DIVU, 0, rx, ry); break; -#if defined (TARGET_MIPS64) +#if defined(TARGET_MIPS64) case RR_DMULT: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); @@ -14802,7 +14806,7 @@ enum { ADDIUR1SP = 0x1 }; -static int mmreg (int r) +static int mmreg(int r) { static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; @@ -14810,7 +14814,7 @@ static int mmreg (int r) } /* Used for 16-bit store instructions. */ -static int mmreg2 (int r) +static int mmreg2(int r) { static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; @@ -14885,8 +14889,8 @@ static void gen_andi16(DisasContext *ctx) gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); } -static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, - int base, int16_t offset) +static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, + int base, int16_t offset) { TCGv t0, t1; TCGv_i32 t2; @@ -15159,7 +15163,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx) } } -static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) +static void gen_ldxs(DisasContext *ctx, int base, int index, int rd) { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -15179,8 +15183,8 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) tcg_temp_free(t1); } -static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, - int base, int16_t offset) +static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, + int base, int16_t offset) { TCGv t0, t1; @@ -15270,7 +15274,7 @@ static void gen_sync(int stype) tcg_gen_mb(tcg_mo); } -static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) +static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) { int extension = (ctx->opcode >> 6) & 0x3f; int minor = (ctx->opcode >> 12) & 0xf; @@ -17234,7 +17238,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) } } -static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) +static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) { uint32_t op; -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] target/mips: Fix some space checkpatch errors in translate.c 2019-06-20 9:19 ` [Qemu-devel] [PATCH 3/4] target/mips: Fix some space checkpatch errors in translate.c Aleksandar Markovic @ 2019-06-20 11:11 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2019-06-20 11:11 UTC (permalink / raw) To: Aleksandar Markovic, qemu-devel; +Cc: arikalo, amarkovic On 6/20/19 11:19 AM, Aleksandar Markovic wrote: > From: Aleksandar Markovic <amarkovic@wavecomp.com> > > Remove some space-related checkpatch warning. > > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/mips/translate.c | 126 +++++++++++++++++++++++++----------------------- > 1 file changed, 65 insertions(+), 61 deletions(-) > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index a3cf976..324b32a 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -2617,7 +2617,7 @@ static const char * const mxuregnames[] = { > } while (0) > > /* General purpose registers moves. */ > -static inline void gen_load_gpr (TCGv t, int reg) > +static inline void gen_load_gpr(TCGv t, int reg) > { > if (reg == 0) > tcg_gen_movi_tl(t, 0); > @@ -2625,14 +2625,14 @@ static inline void gen_load_gpr (TCGv t, int reg) > tcg_gen_mov_tl(t, cpu_gpr[reg]); > } > > -static inline void gen_store_gpr (TCGv t, int reg) > +static inline void gen_store_gpr(TCGv t, int reg) > { > if (reg != 0) > tcg_gen_mov_tl(cpu_gpr[reg], t); > } > > /* Moves to/from shadow registers. */ > -static inline void gen_load_srsgpr (int from, int to) > +static inline void gen_load_srsgpr(int from, int to) > { > TCGv t0 = tcg_temp_new(); > > @@ -2839,7 +2839,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) > } > } > > -static inline int get_fp_bit (int cc) > +static inline int get_fp_bit(int cc) > { > if (cc) > return 24 + cc; > @@ -2848,7 +2848,8 @@ static inline int get_fp_bit (int cc) > } > > /* Addresses computation */ > -static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) > +static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, > + TCGv arg1) > { > tcg_gen_add_tl(ret, arg0, arg1); > > @@ -3328,8 +3329,8 @@ OP_LD_ATOMIC(lld,ld64); > #endif > #undef OP_LD_ATOMIC > > -static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, > - int base, int offset) > +static void gen_base_offset_addr(DisasContext *ctx, TCGv addr, > + int base, int offset) > { > if (base == 0) { > tcg_gen_movi_tl(addr, offset); > @@ -3341,7 +3342,7 @@ static void gen_base_offset_addr (DisasContext *ctx, TCGv addr, > } > } > > -static target_ulong pc_relative_pc (DisasContext *ctx) > +static target_ulong pc_relative_pc(DisasContext *ctx) > { > target_ulong pc = ctx->base.pc_next; > > @@ -3578,8 +3579,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset, > } > > /* Store */ > -static void gen_st (DisasContext *ctx, uint32_t opc, int rt, > - int base, int offset) > +static void gen_st(DisasContext *ctx, uint32_t opc, int rt, > + int base, int offset) > { > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > @@ -3717,8 +3718,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, > } > > /* Load and store */ > -static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, > - TCGv t0) > +static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft, > + TCGv t0) > { > /* Don't do NOP if destination is zero: we must perform the actual > memory access. */ > @@ -5132,8 +5133,8 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, > tcg_temp_free(t1); > } > > -static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, > - int rd, int rs, int rt) > +static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, > + int rd, int rs, int rt) > { > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > @@ -5196,8 +5197,8 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, > tcg_temp_free(t1); > } > > -static void gen_cl (DisasContext *ctx, uint32_t opc, > - int rd, int rs) > +static void gen_cl(DisasContext *ctx, uint32_t opc, > + int rd, int rs) > { > TCGv t0; > > @@ -6188,8 +6189,8 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, > > > /* special3 bitfield operations */ > -static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, > - int rs, int lsb, int msb) > +static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt, > + int rs, int lsb, int msb) > { > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > @@ -6259,7 +6260,7 @@ fail: > tcg_temp_free(t1); > } > > -static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) > +static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) > { > TCGv t0; > > @@ -6502,7 +6503,7 @@ static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) > tcg_temp_free_i64(t0); > } > > -static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) > +static inline void gen_mfc0_load32(TCGv arg, target_ulong off) > { > TCGv_i32 t0 = tcg_temp_new_i32(); > > @@ -6511,13 +6512,13 @@ static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) > tcg_temp_free_i32(t0); > } > > -static inline void gen_mfc0_load64 (TCGv arg, target_ulong off) > +static inline void gen_mfc0_load64(TCGv arg, target_ulong off) > { > tcg_gen_ld_tl(arg, cpu_env, off); > tcg_gen_ext32s_tl(arg, arg); > } > > -static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) > +static inline void gen_mtc0_store32(TCGv arg, target_ulong off) > { > TCGv_i32 t0 = tcg_temp_new_i32(); > > @@ -10077,7 +10078,8 @@ die: > generate_exception_end(ctx, EXCP_RI); > } > > -static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) > +static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, > + int rt, int rd) > { > const char *opn = "ldst"; > > @@ -10633,7 +10635,8 @@ enum r6_f_cmp_op { > R6_OPC_CMP_SUNE_D = FOP(26, FMT_L), > R6_OPC_CMP_SNE_D = FOP(27, FMT_L), > }; > -static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) > + > +static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs) > { > TCGv t0 = tcg_temp_new(); > > @@ -10714,7 +10717,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) > tcg_temp_free(t0); > } > > -static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) > +static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) > { > TCGLabel *l1; > TCGCond cond; > @@ -10763,7 +10766,8 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, > tcg_temp_free_i32(t0); > } > > -static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) > +static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, > + int tf) > { > int cond; > TCGv_i32 t0 = tcg_temp_new_i32(); > @@ -10886,8 +10890,8 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, > tcg_temp_free_i64(t1); > } > > -static void gen_farith (DisasContext *ctx, enum fopcode op1, > - int ft, int fs, int fd, int cc) > +static void gen_farith(DisasContext *ctx, enum fopcode op1, > + int ft, int fs, int fd, int cc) > { > uint32_t func = ctx->opcode & 0x3f; > switch (op1) { > @@ -12314,8 +12318,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, > } > > /* Coprocessor 3 (FPU) */ > -static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, > - int fd, int fs, int base, int index) > +static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc, > + int fd, int fs, int base, int index) > { > TCGv t0 = tcg_temp_new(); > > @@ -12394,8 +12398,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, > tcg_temp_free(t0); > } > > -static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, > - int fd, int fr, int fs, int ft) > +static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, > + int fd, int fr, int fs, int ft) > { > switch (opc) { > case OPC_ALNV_PS: > @@ -13157,17 +13161,17 @@ enum { > RR_RY_CNVT_SEW = 0x6, > }; > > -static int xlat (int r) > +static int xlat(int r) > { > static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; > > return map[r]; > } > > -static void gen_mips16_save (DisasContext *ctx, > - int xsregs, int aregs, > - int do_ra, int do_s0, int do_s1, > - int framesize) > +static void gen_mips16_save(DisasContext *ctx, > + int xsregs, int aregs, > + int do_ra, int do_s0, int do_s1, > + int framesize) > { > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > @@ -13322,10 +13326,10 @@ static void gen_mips16_save (DisasContext *ctx, > tcg_temp_free(t2); > } > > -static void gen_mips16_restore (DisasContext *ctx, > - int xsregs, int aregs, > - int do_ra, int do_s0, int do_s1, > - int framesize) > +static void gen_mips16_restore(DisasContext *ctx, > + int xsregs, int aregs, > + int do_ra, int do_s0, int do_s1, > + int framesize) > { > int astatic; > TCGv t0 = tcg_temp_new(); > @@ -13428,8 +13432,8 @@ static void gen_mips16_restore (DisasContext *ctx, > tcg_temp_free(t2); > } > > -static void gen_addiupc (DisasContext *ctx, int rx, int imm, > - int is_64_bit, int extended) > +static void gen_addiupc(DisasContext *ctx, int rx, int imm, > + int is_64_bit, int extended) > { > TCGv t0; > > @@ -13459,9 +13463,9 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, > } > > #if defined(TARGET_MIPS64) > -static void decode_i64_mips16 (DisasContext *ctx, > - int ry, int funct, int16_t offset, > - int extended) > +static void decode_i64_mips16(DisasContext *ctx, > + int ry, int funct, int16_t offset, > + int extended) > { > switch (funct) { > case I64_LDSP: > @@ -13520,7 +13524,7 @@ static void decode_i64_mips16 (DisasContext *ctx, > } > #endif > > -static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) > +static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx) > { > int extend = cpu_lduw_code(env, ctx->base.pc_next + 2); > int op, rx, ry, funct, sa; > @@ -13734,7 +13738,7 @@ static inline void gen_helper_do_semihosting(void *env) > } > #endif > > -static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) > +static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) > { > int rx, ry; > int sa; > @@ -13957,7 +13961,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) > case M16_OPC_LWPC: > gen_ld(ctx, OPC_LWPC, rx, 0, ((uint8_t)ctx->opcode) << 2); > break; > -#if defined (TARGET_MIPS64) > +#if defined(TARGET_MIPS64) > case M16_OPC_LWU: > check_insn(ctx, ISA_MIPS3); > check_mips_64(ctx); > @@ -14061,7 +14065,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) > case RR_SRAV: > gen_shift(ctx, OPC_SRAV, ry, rx, ry); > break; > -#if defined (TARGET_MIPS64) > +#if defined(TARGET_MIPS64) > case RR_DSRL: > check_insn(ctx, ISA_MIPS3); > check_mips_64(ctx); > @@ -14124,7 +14128,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) > case RR_MFLO: > gen_HILO(ctx, OPC_MFLO, 0, rx); > break; > -#if defined (TARGET_MIPS64) > +#if defined(TARGET_MIPS64) > case RR_DSRA: > check_insn(ctx, ISA_MIPS3); > check_mips_64(ctx); > @@ -14158,7 +14162,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) > case RR_DIVU: > gen_muldiv(ctx, OPC_DIVU, 0, rx, ry); > break; > -#if defined (TARGET_MIPS64) > +#if defined(TARGET_MIPS64) > case RR_DMULT: > check_insn(ctx, ISA_MIPS3); > check_mips_64(ctx); > @@ -14802,7 +14806,7 @@ enum { > ADDIUR1SP = 0x1 > }; > > -static int mmreg (int r) > +static int mmreg(int r) > { > static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 }; > > @@ -14810,7 +14814,7 @@ static int mmreg (int r) > } > > /* Used for 16-bit store instructions. */ > -static int mmreg2 (int r) > +static int mmreg2(int r) > { > static const int map[] = { 0, 17, 2, 3, 4, 5, 6, 7 }; > > @@ -14885,8 +14889,8 @@ static void gen_andi16(DisasContext *ctx) > gen_logic_imm(ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); > } > > -static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, > - int base, int16_t offset) > +static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist, > + int base, int16_t offset) > { > TCGv t0, t1; > TCGv_i32 t2; > @@ -15159,7 +15163,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx) > } > } > > -static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) > +static void gen_ldxs(DisasContext *ctx, int base, int index, int rd) > { > TCGv t0 = tcg_temp_new(); > TCGv t1 = tcg_temp_new(); > @@ -15179,8 +15183,8 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) > tcg_temp_free(t1); > } > > -static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, > - int base, int16_t offset) > +static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd, > + int base, int16_t offset) > { > TCGv t0, t1; > > @@ -15270,7 +15274,7 @@ static void gen_sync(int stype) > tcg_gen_mb(tcg_mo); > } > > -static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) > +static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs) > { > int extension = (ctx->opcode >> 6) & 0x3f; > int minor = (ctx->opcode >> 12) & 0xf; > @@ -17234,7 +17238,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) > } > } > > -static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) > +static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx) > { > uint32_t op; > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms checkpatch errors in translate.c 2019-06-20 9:19 [Qemu-devel] [PATCH 0/4] target/mips: Misc fixes and maintenance for 4.1 Aleksandar Markovic ` (2 preceding siblings ...) 2019-06-20 9:19 ` [Qemu-devel] [PATCH 3/4] target/mips: Fix some space checkpatch errors in translate.c Aleksandar Markovic @ 2019-06-20 9:19 ` Aleksandar Markovic 2019-06-20 11:11 ` Philippe Mathieu-Daudé 3 siblings, 1 reply; 8+ messages in thread From: Aleksandar Markovic @ 2019-06-20 9:19 UTC (permalink / raw) To: qemu-devel; +Cc: arikalo, amarkovic From: Aleksandar Markovic <amarkovic@wavecomp.com> Remove if-else-arms-related checkpatch errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> --- target/mips/translate.c | 106 ++++++++++++++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 40 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 324b32a..3558b2e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2619,16 +2619,18 @@ static const char * const mxuregnames[] = { /* General purpose registers moves. */ static inline void gen_load_gpr(TCGv t, int reg) { - if (reg == 0) + if (reg == 0) { tcg_gen_movi_tl(t, 0); - else + } else { tcg_gen_mov_tl(t, cpu_gpr[reg]); + } } static inline void gen_store_gpr(TCGv t, int reg) { - if (reg != 0) + if (reg != 0) { tcg_gen_mov_tl(cpu_gpr[reg], t); + } } /* Moves to/from shadow registers. */ @@ -2636,9 +2638,9 @@ static inline void gen_load_srsgpr(int from, int to) { TCGv t0 = tcg_temp_new(); - if (from == 0) + if (from == 0) { tcg_gen_movi_tl(t0, 0); - else { + } else { TCGv_i32 t2 = tcg_temp_new_i32(); TCGv_ptr addr = tcg_temp_new_ptr(); @@ -2841,10 +2843,11 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) static inline int get_fp_bit(int cc) { - if (cc) + if (cc) { return 24 + cc; - else + } else { return 23; + } } /* Addresses computation */ @@ -2908,14 +2911,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg) static inline void check_cp0_enabled(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { generate_exception_err(ctx, EXCP_CpU, 0); + } } static inline void check_cp1_enabled(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); + } } /* Verify that the processor is running with COP1X instructions enabled. @@ -2924,8 +2929,9 @@ static inline void check_cp1_enabled(DisasContext *ctx) static inline void check_cop1x(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { generate_exception_end(ctx, EXCP_RI); + } } /* Verify that the processor is running with 64-bit floating-point @@ -2933,8 +2939,9 @@ static inline void check_cop1x(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx) { - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { generate_exception_end(ctx, EXCP_RI); + } } /* @@ -2950,8 +2957,9 @@ static inline void check_cp1_64bitmode(DisasContext *ctx) */ static inline void check_cp1_registers(DisasContext *ctx, int regs) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { generate_exception_end(ctx, EXCP_RI); + } } /* Verify that the processor is running with DSP instructions enabled. @@ -3040,8 +3048,9 @@ static inline void check_ps(DisasContext *ctx) instructions are not enabled. */ static inline void check_mips_64(DisasContext *ctx) { - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { generate_exception_end(ctx, EXCP_RI); + } } #endif @@ -3131,8 +3140,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && - !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) - { + !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) { generate_exception_end(ctx, EXCP_RI); } } @@ -3882,22 +3890,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc, uimm = (uint16_t)imm; switch (opc) { case OPC_ANDI: - if (likely(rs != 0)) + if (likely(rs != 0)) { tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], 0); + } break; case OPC_ORI: - if (rs != 0) + if (rs != 0) { tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } break; case OPC_XORI: - if (likely(rs != 0)) + if (likely(rs != 0)) { tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); - else + } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); + } break; case OPC_LUI: if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) { @@ -6060,8 +6071,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, } out: - if (insn_bytes == 2) + if (insn_bytes == 2) { ctx->hflags |= MIPS_HFLAG_B16; + } tcg_temp_free(t0); tcg_temp_free(t1); } @@ -6708,8 +6720,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name = "invalid"; - if (sel != 0) + if (sel != 0) { check_insn(ctx, ISA_MIPS32); + } switch (reg) { case CP0_REGISTER_00: @@ -7464,8 +7477,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name = "invalid"; - if (sel != 0) + if (sel != 0) { check_insn(ctx, ISA_MIPS32); + } if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -8210,8 +8224,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name = "invalid"; - if (sel != 0) + if (sel != 0) { check_insn(ctx, ISA_MIPS64); + } switch (reg) { case CP0_REGISTER_00: @@ -8920,8 +8935,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name = "invalid"; - if (sel != 0) + if (sel != 0) { check_insn(ctx, ISA_MIPS64); + } if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -10162,8 +10178,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_TLBWI: opn = "tlbwi"; - if (!env->tlb->helper_tlbwi) + if (!env->tlb->helper_tlbwi) { goto die; + } gen_helper_tlbwi(cpu_env); break; case OPC_TLBINV: @@ -10186,20 +10203,23 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_TLBWR: opn = "tlbwr"; - if (!env->tlb->helper_tlbwr) + if (!env->tlb->helper_tlbwr) { goto die; + } gen_helper_tlbwr(cpu_env); break; case OPC_TLBP: opn = "tlbp"; - if (!env->tlb->helper_tlbp) + if (!env->tlb->helper_tlbp) { goto die; + } gen_helper_tlbp(cpu_env); break; case OPC_TLBR: opn = "tlbr"; - if (!env->tlb->helper_tlbr) + if (!env->tlb->helper_tlbr) { goto die; + } gen_helper_tlbr(cpu_env); break; case OPC_ERET: /* OPC_ERETNC */ @@ -10273,8 +10293,9 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, goto out; } - if (cc != 0) + if (cc != 0) { check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); + } btarget = ctx->base.pc_next + 4 + offset; @@ -10728,10 +10749,11 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) return; } - if (tf) + if (tf) { cond = TCG_COND_EQ; - else + } else { cond = TCG_COND_NE; + } l1 = gen_new_label(); t0 = tcg_temp_new_i32(); @@ -10753,10 +10775,11 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, TCGv_i32 t0 = tcg_temp_new_i32(); TCGLabel *l1 = gen_new_label(); - if (tf) + if (tf) { cond = TCG_COND_EQ; - else + } else { cond = TCG_COND_NE; + } tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -10774,10 +10797,11 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, TCGv_i64 fp0; TCGLabel *l1 = gen_new_label(); - if (tf) + if (tf) { cond = TCG_COND_EQ; - else + } else { cond = TCG_COND_NE; + } tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -10797,10 +10821,11 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); - if (tf) + if (tf) { cond = TCG_COND_EQ; - else + } else { cond = TCG_COND_NE; + } tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); @@ -12096,8 +12121,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, TCGLabel *l1 = gen_new_label(); TCGv_i64 fp0; - if (ft != 0) + if (ft != 0) { tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); + } fp0 = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); -- 2.7.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms checkpatch errors in translate.c 2019-06-20 9:19 ` [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms " Aleksandar Markovic @ 2019-06-20 11:11 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2019-06-20 11:11 UTC (permalink / raw) To: Aleksandar Markovic, qemu-devel; +Cc: arikalo, amarkovic On 6/20/19 11:19 AM, Aleksandar Markovic wrote: > From: Aleksandar Markovic <amarkovic@wavecomp.com> > > Remove if-else-arms-related checkpatch errors. > > Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/mips/translate.c | 106 ++++++++++++++++++++++++++++++------------------ > 1 file changed, 66 insertions(+), 40 deletions(-) > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index 324b32a..3558b2e 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -2619,16 +2619,18 @@ static const char * const mxuregnames[] = { > /* General purpose registers moves. */ > static inline void gen_load_gpr(TCGv t, int reg) > { > - if (reg == 0) > + if (reg == 0) { > tcg_gen_movi_tl(t, 0); > - else > + } else { > tcg_gen_mov_tl(t, cpu_gpr[reg]); > + } > } > > static inline void gen_store_gpr(TCGv t, int reg) > { > - if (reg != 0) > + if (reg != 0) { > tcg_gen_mov_tl(cpu_gpr[reg], t); > + } > } > > /* Moves to/from shadow registers. */ > @@ -2636,9 +2638,9 @@ static inline void gen_load_srsgpr(int from, int to) > { > TCGv t0 = tcg_temp_new(); > > - if (from == 0) > + if (from == 0) { > tcg_gen_movi_tl(t0, 0); > - else { > + } else { > TCGv_i32 t2 = tcg_temp_new_i32(); > TCGv_ptr addr = tcg_temp_new_ptr(); > > @@ -2841,10 +2843,11 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) > > static inline int get_fp_bit(int cc) > { > - if (cc) > + if (cc) { > return 24 + cc; > - else > + } else { > return 23; > + } > } > > /* Addresses computation */ > @@ -2908,14 +2911,16 @@ static inline void gen_move_high32(TCGv ret, TCGv_i64 arg) > > static inline void check_cp0_enabled(DisasContext *ctx) > { > - if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) > + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { > generate_exception_err(ctx, EXCP_CpU, 0); > + } > } > > static inline void check_cp1_enabled(DisasContext *ctx) > { > - if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) > + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { > generate_exception_err(ctx, EXCP_CpU, 1); > + } > } > > /* Verify that the processor is running with COP1X instructions enabled. > @@ -2924,8 +2929,9 @@ static inline void check_cp1_enabled(DisasContext *ctx) > > static inline void check_cop1x(DisasContext *ctx) > { > - if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) > + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { > generate_exception_end(ctx, EXCP_RI); > + } > } > > /* Verify that the processor is running with 64-bit floating-point > @@ -2933,8 +2939,9 @@ static inline void check_cop1x(DisasContext *ctx) > > static inline void check_cp1_64bitmode(DisasContext *ctx) > { > - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) > + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { > generate_exception_end(ctx, EXCP_RI); > + } > } > > /* > @@ -2950,8 +2957,9 @@ static inline void check_cp1_64bitmode(DisasContext *ctx) > */ > static inline void check_cp1_registers(DisasContext *ctx, int regs) > { > - if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) > + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { > generate_exception_end(ctx, EXCP_RI); > + } > } > > /* Verify that the processor is running with DSP instructions enabled. > @@ -3040,8 +3048,9 @@ static inline void check_ps(DisasContext *ctx) > instructions are not enabled. */ > static inline void check_mips_64(DisasContext *ctx) > { > - if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) > + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) { > generate_exception_end(ctx, EXCP_RI); > + } > } > #endif > > @@ -3131,8 +3140,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx) > !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && > !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && > !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && > - !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) > - { > + !(ctx->CP0_Config5 & (1 << CP0C5_L2C))) { > generate_exception_end(ctx, EXCP_RI); > } > } > @@ -3882,22 +3890,25 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc, > uimm = (uint16_t)imm; > switch (opc) { > case OPC_ANDI: > - if (likely(rs != 0)) > + if (likely(rs != 0)) { > tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); > - else > + } else { > tcg_gen_movi_tl(cpu_gpr[rt], 0); > + } > break; > case OPC_ORI: > - if (rs != 0) > + if (rs != 0) { > tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); > - else > + } else { > tcg_gen_movi_tl(cpu_gpr[rt], uimm); > + } > break; > case OPC_XORI: > - if (likely(rs != 0)) > + if (likely(rs != 0)) { > tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); > - else > + } else { > tcg_gen_movi_tl(cpu_gpr[rt], uimm); > + } > break; > case OPC_LUI: > if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) { > @@ -6060,8 +6071,9 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > } > > out: > - if (insn_bytes == 2) > + if (insn_bytes == 2) { > ctx->hflags |= MIPS_HFLAG_B16; > + } > tcg_temp_free(t0); > tcg_temp_free(t1); > } > @@ -6708,8 +6720,9 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) > { > const char *register_name = "invalid"; > > - if (sel != 0) > + if (sel != 0) { > check_insn(ctx, ISA_MIPS32); > + } > > switch (reg) { > case CP0_REGISTER_00: > @@ -7464,8 +7477,9 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) > { > const char *register_name = "invalid"; > > - if (sel != 0) > + if (sel != 0) { > check_insn(ctx, ISA_MIPS32); > + } > > if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { > gen_io_start(); > @@ -8210,8 +8224,9 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) > { > const char *register_name = "invalid"; > > - if (sel != 0) > + if (sel != 0) { > check_insn(ctx, ISA_MIPS64); > + } > > switch (reg) { > case CP0_REGISTER_00: > @@ -8920,8 +8935,9 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) > { > const char *register_name = "invalid"; > > - if (sel != 0) > + if (sel != 0) { > check_insn(ctx, ISA_MIPS64); > + } > > if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { > gen_io_start(); > @@ -10162,8 +10178,9 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, > break; > case OPC_TLBWI: > opn = "tlbwi"; > - if (!env->tlb->helper_tlbwi) > + if (!env->tlb->helper_tlbwi) { > goto die; > + } > gen_helper_tlbwi(cpu_env); > break; > case OPC_TLBINV: > @@ -10186,20 +10203,23 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, > break; > case OPC_TLBWR: > opn = "tlbwr"; > - if (!env->tlb->helper_tlbwr) > + if (!env->tlb->helper_tlbwr) { > goto die; > + } > gen_helper_tlbwr(cpu_env); > break; > case OPC_TLBP: > opn = "tlbp"; > - if (!env->tlb->helper_tlbp) > + if (!env->tlb->helper_tlbp) { > goto die; > + } > gen_helper_tlbp(cpu_env); > break; > case OPC_TLBR: > opn = "tlbr"; > - if (!env->tlb->helper_tlbr) > + if (!env->tlb->helper_tlbr) { > goto die; > + } > gen_helper_tlbr(cpu_env); > break; > case OPC_ERET: /* OPC_ERETNC */ > @@ -10273,8 +10293,9 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, > goto out; > } > > - if (cc != 0) > + if (cc != 0) { > check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); > + } > > btarget = ctx->base.pc_next + 4 + offset; > > @@ -10728,10 +10749,11 @@ static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) > return; > } > > - if (tf) > + if (tf) { > cond = TCG_COND_EQ; > - else > + } else { > cond = TCG_COND_NE; > + } > > l1 = gen_new_label(); > t0 = tcg_temp_new_i32(); > @@ -10753,10 +10775,11 @@ static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc, > TCGv_i32 t0 = tcg_temp_new_i32(); > TCGLabel *l1 = gen_new_label(); > > - if (tf) > + if (tf) { > cond = TCG_COND_EQ; > - else > + } else { > cond = TCG_COND_NE; > + } > > tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); > tcg_gen_brcondi_i32(cond, t0, 0, l1); > @@ -10774,10 +10797,11 @@ static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, > TCGv_i64 fp0; > TCGLabel *l1 = gen_new_label(); > > - if (tf) > + if (tf) { > cond = TCG_COND_EQ; > - else > + } else { > cond = TCG_COND_NE; > + } > > tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); > tcg_gen_brcondi_i32(cond, t0, 0, l1); > @@ -10797,10 +10821,11 @@ static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd, > TCGLabel *l1 = gen_new_label(); > TCGLabel *l2 = gen_new_label(); > > - if (tf) > + if (tf) { > cond = TCG_COND_EQ; > - else > + } else { > cond = TCG_COND_NE; > + } > > tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); > tcg_gen_brcondi_i32(cond, t0, 0, l1); > @@ -12096,8 +12121,9 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1, > TCGLabel *l1 = gen_new_label(); > TCGv_i64 fp0; > > - if (ft != 0) > + if (ft != 0) { > tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); > + } > fp0 = tcg_temp_new_i64(); > gen_load_fpr64(ctx, fp0, fs); > gen_store_fpr64(ctx, fp0, fd); > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-06-20 11:34 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-06-20 9:19 [Qemu-devel] [PATCH 0/4] target/mips: Misc fixes and maintenance for 4.1 Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 1/4] MAINTAINERS: Update file items for MIPS Malta board Aleksandar Markovic 2019-06-20 11:13 ` Philippe Mathieu-Daudé 2019-06-20 9:19 ` [Qemu-devel] [PATCH 2/4] MAINTAINERS: Consolidate MIPS disassembler-related items Aleksandar Markovic 2019-06-20 9:19 ` [Qemu-devel] [PATCH 3/4] target/mips: Fix some space checkpatch errors in translate.c Aleksandar Markovic 2019-06-20 11:11 ` Philippe Mathieu-Daudé 2019-06-20 9:19 ` [Qemu-devel] [PATCH 4/4] target/mips: Fix if-else arms " Aleksandar Markovic 2019-06-20 11:11 ` Philippe Mathieu-Daudé
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