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([2602:47:d490:6901:a7b4:380e:e513:5ef2]) by smtp.gmail.com with ESMTPSA id o2-20020a639202000000b00563397f1624sm6668168pgd.69.2023.07.30.10.43.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Jul 2023 10:43:48 -0700 (PDT) Message-ID: <19b913a1-57d1-1631-06bb-04149b8a7bd1@linaro.org> Date: Sun, 30 Jul 2023 10:43:45 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH] target/openrisc: Set EPCR to next PC on FPE exceptions Content-Language: en-US To: Stafford Horne , QEMU Development References: <20230729210851.3097340-1-shorne@gmail.com> From: Richard Henderson In-Reply-To: <20230729210851.3097340-1-shorne@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.101, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/29/23 14:08, Stafford Horne wrote: > The architecture specification calls for the EPCR to be set to "Address > of next not executed instruction" when there is a floating point > exception (FPE). This was not being done, so fix it by using the same > method as syscall. Note, this may need a lot more work if we start > seeing floating point operations in delay slots which exceptions > enabled. > > Without this patch FPU exceptions will loop, as the exception hanlding > will always return back to the failed floating point instruction. > > This was not noticed in earlier testing because: > > 1. The compiler usually generates code which clobbers the input operand > such as: > > lf.div.s r19,r17,r19 > > 2. The target will store the operation output before to the register > before handling the exception. So an operation such as: > > float a = 100.0f; > float b = 0.0f; > float c = a / b; /* lf.div.s r19,r17,r19 */ > > Will first execute: > > 100 / 0 -> Store inf to c (r19) > -> triggering divide by zero exception > -> handle and return > > Then it will exectute: > > 100 / inf -> Store 0 to c (no exception) > > To confirm the looping behavoid and the fix I used the following: > > float fpu_div(float a, float b) { > float c; > asm volatile("lf.div.s %0, %1, %2" > : "+r" (c) > : "r" (a), "r" (b)); > return c; > } > > Signed-off-by: Stafford Horne > --- > target/openrisc/interrupt.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c > index 3887812810..9b14b8a2c6 100644 > --- a/target/openrisc/interrupt.c > +++ b/target/openrisc/interrupt.c > @@ -34,7 +34,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) > int exception = cs->exception_index; > > env->epcr = env->pc; > - if (exception == EXCP_SYSCALL) { > + if (exception == EXCP_SYSCALL || exception == EXCP_FPE) { > env->epcr += 4; > } > /* When we have an illegal instruction the error effective address According to Table 6-3, when in a delay slot the EPCR should be the address of the jump, for both syscall and fpe. This whole block should be moved down... > /* Set/clear dsx to indicate if we are in a delay slot exception. */ > if (env->dflag) { > env->dflag = 0; > env->sr |= SR_DSX; > env->epcr -= 4; > } else { > env->sr &= ~SR_DSX; > } ... into the else. With that, Reviewed-by: Richard Henderson r~