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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Fabiano Rosas <farosas@suse.de>
Subject: Re: [RFC PATCH 1/5] target/ppc: gdbstub init spr gdb_id for all CPUs
Date: Wed, 31 May 2023 07:49:06 +0200	[thread overview]
Message-ID: <19c434db-b1ac-656d-474f-938cdbf96fcd@linaro.org> (raw)
In-Reply-To: <20230531012313.19891-2-npiggin@gmail.com>

On 31/5/23 03:23, Nicholas Piggin wrote:
> Make sure each CPU gets its state set up for gdb, not just the ones
> before PowerPCCPUClass has had its gdb state set up.
> 

Cc: qemu-stable@nongnu.org
Fixes: 707c7c2ee1 ("target/ppc: Enable reporting of SPRs to GDB")

> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   target/ppc/gdbstub.c | 30 +++++++++++++++++++-----------
>   1 file changed, 19 insertions(+), 11 deletions(-)
> 
> diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
> index 63c9abe4f1..ca39efdc35 100644
> --- a/target/ppc/gdbstub.c
> +++ b/target/ppc/gdbstub.c
> @@ -327,6 +327,25 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
>       unsigned int num_regs = 0;
>       int i;
>   
> +    for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
> +        ppc_spr_t *spr = &env->spr_cb[i];
> +
> +        if (!spr->name) {
> +            continue;
> +        }
> +
> +        /*
> +         * GDB identifies registers based on the order they are
> +         * presented in the XML. These ids will not match QEMU's
> +         * representation (which follows the PowerISA).
> +         *
> +         * Store the position of the current register description so
> +         * we can make the correspondence later.
> +         */
> +        spr->gdb_id = num_regs;
> +        num_regs++;
> +    }
> +
>       if (pcc->gdb_spr_xml) {
>           return;
>       }
> @@ -348,17 +367,6 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
>   
>           g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
>           g_string_append(xml, " group=\"spr\"/>");
> -
> -        /*
> -         * GDB identifies registers based on the order they are
> -         * presented in the XML. These ids will not match QEMU's
> -         * representation (which follows the PowerISA).
> -         *
> -         * Store the position of the current register description so
> -         * we can make the correspondence later.
> -         */
> -        spr->gdb_id = num_regs;
> -        num_regs++;
>       }
>   
>       g_string_append(xml, "</feature>");

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



  reply	other threads:[~2023-05-31  5:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-31  1:23 [RFC PATCH 0/5] target/ppc: initial SMT support in TCG Nicholas Piggin
2023-05-31  1:23 ` [RFC PATCH 1/5] target/ppc: gdbstub init spr gdb_id for all CPUs Nicholas Piggin
2023-05-31  5:49   ` Philippe Mathieu-Daudé [this message]
2023-06-23  9:26   ` Cédric Le Goater
2023-05-31  1:23 ` [RFC PATCH 2/5] target/ppc: Add initial flags and helpers for SMT support Nicholas Piggin
2023-05-31  7:25   ` Cédric Le Goater
2023-06-02  6:54     ` Nicholas Piggin
2023-05-31  1:23 ` [RFC PATCH 3/5] target/ppc: Add support for SMT CTRL register Nicholas Piggin
2023-05-31  1:23 ` [RFC PATCH 4/5] target/ppc: Add msgsnd/p and DPDES SMT support Nicholas Piggin
2023-06-01  7:13   ` Cédric Le Goater
2023-06-02  6:56     ` Nicholas Piggin
2023-05-31  1:23 ` [RFC PATCH 5/5] spapr: Allow up to 8 threads SMT configuration Nicholas Piggin
2023-06-01  7:20   ` Cédric Le Goater
2023-06-02  6:59     ` Nicholas Piggin
2023-06-02  7:04       ` Cédric Le Goater
2023-06-05 10:29     ` Nicholas Piggin
2023-06-01  7:56 ` [RFC PATCH 0/5] target/ppc: initial SMT support in TCG Cédric Le Goater
2023-06-02  7:01   ` Nicholas Piggin
2023-06-02  7:21     ` Cédric Le Goater

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