From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support
Date: Wed, 19 Dec 2018 22:07:07 -0800 [thread overview]
Message-ID: <19f7305e-ae63-3a5b-87dd-e0cfd835462f@linaro.org> (raw)
In-Reply-To: <cover.1545246859.git.alistair.francis@wdc.com>
On 12/19/18 11:16 AM, Alistair Francis wrote:
> This patch set adds RISC-V backend support to QEMU. This is based on
> Michael Clark's original work with extra work on top.
>
> This has been somewhat tested and can run other architecture softmmu
> code. It seems that any complex OS will eventually hang, but we can
> run the BIOS and OS startup code for a number of different operating
> systems.
>
> I haven't tested linux user support at all yet. I think Michael had that
> working reliably though and hopefully my changes haven't broken it.
>
> There are still some todos in the code (there are missing instructions
> and byte swapping) but these should assert instead of generating invalid
> code.
Queued to tcg-next, with the extrh fix.
Some of those todos are no longer todos, since e.g. bswap is now optional.
Those asserts should never fire (as a good assert should do, I suppose).
The missing instructions are only for riscv32, which afaik is just now making
its way to glibc. So a chroot complete enough to build qemu is a ways away.
I'm ok with leaving that incomplete for now.
r~
next prev parent reply other threads:[~2018-12-20 6:07 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-19 19:16 [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support Alistair Francis
2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis
2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis
2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis
2018-12-19 19:16 ` [Qemu-devel] [PATCH v2 04/23] exec: Add RISC-V GCC poison macro Alistair Francis
2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 05/23] riscv: Add the tcg-target header file Alistair Francis
2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 06/23] riscv: Add the tcg target registers Alistair Francis
2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 07/23] riscv: tcg-target: Add support for the constraints Alistair Francis
2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 08/23] riscv: tcg-target: Add the immediate encoders Alistair Francis
2018-12-19 19:17 ` [Qemu-devel] [PATCH v2 09/23] riscv: tcg-target: Add the instruction emitters Alistair Francis
2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 10/23] riscv: tcg-target: Add the relocation functions Alistair Francis
2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 11/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis
2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 12/23] riscv: tcg-target: Add the extract instructions Alistair Francis
2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 13/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis
2018-12-19 19:18 ` [Qemu-devel] [PATCH v2 14/23] riscv: tcg-target: Add the add2 and sub2 instructions Alistair Francis
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 17/23] riscv: tcg-target: Add direct " Alistair Francis
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis
2018-12-20 5:59 ` Richard Henderson
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 19/23] riscv: tcg-target: Add the prologue generation and register the JIT Alistair Francis
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 20/23] riscv: tcg-target: Add the target init code Alistair Francis
2018-12-19 19:19 ` [Qemu-devel] [PATCH v2 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis
2018-12-19 19:20 ` [Qemu-devel] [PATCH v2 22/23] dias: Add RISC-V support Alistair Francis
2018-12-19 19:20 ` [Qemu-devel] [PATCH v2 23/23] configure: Add support for building RISC-V host Alistair Francis
2018-12-20 6:07 ` Richard Henderson [this message]
2018-12-20 17:20 ` [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support Alistair Francis
2018-12-20 18:45 ` Palmer Dabbelt
2018-12-20 19:04 ` Alistair Francis
2018-12-20 19:10 ` Palmer Dabbelt
2018-12-25 14:44 ` no-reply
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