Re: [PATCH v13 5/5] qtest/cxl: Add aarch64 virt test for CXL

[Itaru Kitayama <itaru.kitayama@linux.dev>]

Jonathan,

> On May 19, 2025, at 21:54, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> 
> On Thu, 15 May 2025 18:04:18 +0900
> Itaru Kitayama <itaru.kitayama@linux.dev> wrote:
> 
>>> On May 13, 2025, at 20:14, Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
>>> 
>>> Add a single complex case for aarch64 virt machine.
>>> Given existing much more comprehensive tests for x86 cover the
>>> common functionality, a single test should be enough to verify
>>> that the aarch64 part continue to work.
>>> 
>>> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>>> ---
>>> tests/qtest/cxl-test.c  | 59 ++++++++++++++++++++++++++++++++---------
>>> tests/qtest/meson.build |  1 +
>>> 2 files changed, 47 insertions(+), 13 deletions(-)
>>> 
>>> diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
>>> index a600331843..c7189d6222 100644
>>> --- a/tests/qtest/cxl-test.c
>>> +++ b/tests/qtest/cxl-test.c
>>> @@ -19,6 +19,12 @@
>>>    "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
>>>    "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
>>> 
>>> +#define QEMU_VIRT_2PXB_CMD \
>>> +    "-machine virt,cxl=on -cpu max " \
>>> +    "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
>>> +    "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
>>> +    "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
>>> +
>>> #define QEMU_RP \
>>>    "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
>>> 
>>> @@ -197,25 +203,52 @@ static void cxl_2pxb_4rp_4t3d(void)
>>>    qtest_end();
>>>    rmdir(tmpfs);
>>> }
>>> +
>>> +static void cxl_virt_2pxb_4rp_4t3d(void)
>>> +{
>>> +    g_autoptr(GString) cmdline = g_string_new(NULL);
>>> +    char template[] = "/tmp/cxl-test-XXXXXX";
>>> +    const char *tmpfs;
>>> +
>>> +    tmpfs = mkdtemp(template);
>>> +
>>> +    g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D,
>>> +                    tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs,
>>> +                    tmpfs, tmpfs);
>>> +
>>> +    qtest_start(cmdline->str);
>>> +    qtest_end();
>>> +    rmdir(tmpfs);
>>> +}
>>> #endif /* CONFIG_POSIX */
>>> 
>>> int main(int argc, char **argv)
>>> {
>>> -    g_test_init(&argc, &argv, NULL);
>>> +    const char *arch = qtest_get_arch();
>>> 
>>> -    qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
>>> -    qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
>>> -    qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
>>> -    qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
>>> -    qtest_add_func("/pci/cxl/rp", cxl_root_port);
>>> -    qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
>>> +    g_test_init(&argc, &argv, NULL);
>>> +    if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
>>> +        qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
>>> +        qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
>>> +        qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
>>> +        qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
>>> +        qtest_add_func("/pci/cxl/rp", cxl_root_port);
>>> +        qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
>>> #ifdef CONFIG_POSIX
>>> -    qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated);
>>> -    qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent);
>>> -    qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile);
>>> -    qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa);
>>> -    qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
>>> -    qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
>>> +        qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated);
>>> +        qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent);
>>> +        qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile);
>>> +        qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa);
>>> +        qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
>>> +        qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4",
>>> +                       cxl_2pxb_4rp_4t3d);
>>> #endif
>>> +    } else if (strcmp(arch, "aarch64") == 0) {
>>> +#ifdef CONFIG_POSIX
>>> +        qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4",
>>> +                       cxl_virt_2pxb_4rp_4t3d);
>>> +#endif
>>> +    }
>>> +
>>>    return g_test_run();
>>> }
>>> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
>>> index 7daf619845..361000267a 100644
>>> --- a/tests/qtest/meson.build
>>> +++ b/tests/qtest/meson.build
>>> @@ -258,6 +258,7 @@ qtests_aarch64 = \
>>>  (config_all_accel.has_key('CONFIG_TCG') and                                            \
>>>   config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
>>>  (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \
>>> +  qtests_cxl +                                                                                  \
>>>  ['arm-cpu-features',
>>>   'numa-test',
>>>   'boot-serial-test',
>>> -- 
>>> 2.43.0
>>> 
>> 
>> ~/projects/qemu/build$ meson test qtest-aarch64/cxl-test
>> ninja: Entering directory `/home/realm/projects/qemu/build'
>> [1/8] Generating qemu-version.h with a custom command (wrapped by meson to capture output)
>> 1/1 qemu:qtest+qtest-aarch64 / qtest-aarch64/cxl-test        OK              0.17s   1 subtests passed
>> 
>> Ok:                 1
>> Expected Fail:      0
>> Fail:               0
>> Unexpected Pass:    0
>> Skipped:            0
>> Timeout:            0
>> 
>> Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com <mailto:itaru.kitayama@fujitsu.com>>
>> 
>> Jonathan, would you push your branch this series applied? I manually applied your series no issues though.
> 
> I'm reluctant to push a 'normal' staging CXL tree whilst we have the TCG
> issue outstanding (which is in mainline).
> I can probably push one with a name that makes it clear we know it will
> crash under some circumstances though. I'll aim to get that done later this week.

Okay, and understood.

> 
> After talking to Richard Henderson I'm going to spin some images etc to
> make it easier for him to replicate that TCG issue.
> 
> Thanks for reviews.

The comments are from Zhijian.

Itaru.

> 
> Jonathan
> 
>> 
>> 
>