From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41027) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuUBo-00022X-1M for qemu-devel@nongnu.org; Tue, 10 Jun 2014 18:06:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuUBe-0006ou-T5 for qemu-devel@nongnu.org; Tue, 10 Jun 2014 18:06:43 -0400 Received: from edge20.ethz.ch ([82.130.99.26]:58279) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuUBe-0006og-JY for qemu-devel@nongnu.org; Tue, 10 Jun 2014 18:06:34 -0400 From: "Aggeler Fabian" Date: Tue, 10 Jun 2014 22:06:31 +0000 Message-ID: <1CDE2CAF-2506-436F-95F4-157B5E5EC8AC@ethz.ch> References: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com> <1402326269-8573-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1402326269-8573-9-git-send-email-edgar.iglesias@gmail.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-ID: <36ABF4F490A21447B3B542E6BEBEB2FE@intern.ethz.ch> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v2 08/17] target-arm: Add SCR_EL3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: "peter.maydell@linaro.org" , "peter.crosthwaite@xilinx.com" , "rob.herring@linaro.org" , "qemu-devel@nongnu.org" , "agraf@suse.de" , "blauwirbel@gmail.com" , "john.williams@xilinx.com" , "greg.bellows@linaro.org" , "pbonzini@redhat.com" , "alex.bennee@linaro.org" , "christoffer.dall@linaro.org" , "rth@twiddle.net" On 09 Jun 2014, at 17:04, Edgar E. Iglesias wrot= e: > From: "Edgar E. Iglesias" >=20 > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 15 +++++++++++++++ > target-arm/helper.c | 29 +++++++++++++++++++++++++++++ > 2 files changed, 44 insertions(+) >=20 > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index cd8c9a7..111577c 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -185,6 +185,7 @@ typedef struct CPUARMState { > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > uint64_t hcr_el2; /* Hypervisor configuration register */ > + uint32_t scr_el3; /* Secure configuration register. */ Is there a reason why we cannot map the Aarch32 SCR (c1_scr) to SCR_EL3?=20 Otherwise I suggest removing the existing c1_scr in this patch and adjustin= g the=20 .fieldoffset of the Aarch32 SCR register definition. Best, Fabian > uint32_t ifsr_el2; /* Fault status registers. */ > uint64_t esr_el[4]; > uint32_t c6_region[8]; /* MPU base/size registers. */ > @@ -561,6 +562,20 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) > #define HCR_ID (1ULL << 33) > #define HCR_MASK ((1ULL << 34) - 1) >=20 > +#define SCR_NS (1U << 0) > +#define SCR_IRQ (1U << 1) > +#define SCR_FIQ (1U << 2) > +#define SCR_EA (1U << 3) > +#define SCR_SMD (1U << 7) > +#define SCR_HCE (1U << 8) > +#define SCR_SIF (1U << 9) > +#define SCR_RW (1U << 10) > +#define SCR_ST (1U << 11) > +#define SCR_TWI (1U << 12) > +#define SCR_TWE (1U << 13) > +#define SCR_RES1_MASK (3U << 4) > +#define SCR_MASK (0x3fff & ~SCR_RES1_MASK) > + > /* Return the current FPSCR value. */ > uint32_t vfp_get_fpscr(CPUARMState *env); > void vfp_set_fpscr(CPUARMState *env, uint32_t val); > diff --git a/target-arm/helper.c b/target-arm/helper.c > index d28951a..17cf80e 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2162,6 +2162,31 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] =3D = { > REGINFO_SENTINEL > }; >=20 > +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t= value) > +{ > + uint32_t valid_mask =3D SCR_MASK; > + > + if (!arm_feature(env, ARM_FEATURE_EL2)) { > + valid_mask &=3D ~SCR_HCE; > + > + /* On ARMv7, SMD (or SCD as it is called in v7) is only > + * supported if EL2 exists. The bit is UNK/SBZP when > + * EL2 is unavailable. In QEMU ARMv7, we force it to always zero > + * when EL2 is unavailable. > + */ > + if (arm_feature(env, ARM_FEATURE_V7)) { > + valid_mask &=3D ~SCR_SMD; > + } > + } > + > + /* Set RES1 bits. */ > + value |=3D SCR_RES1_MASK; > + > + /* Clear RES0 bits. */ > + value &=3D valid_mask; > + raw_write(env, ri, value); > +} > + > static const ARMCPRegInfo v8_el3_cp_reginfo[] =3D { > { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, > .type =3D ARM_CP_NO_MIGRATE, > @@ -2184,6 +2209,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] =3D = { > .access =3D PL3_RW, .writefn =3D vbar_write, > .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), > .resetvalue =3D 0 }, > + { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, > + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, > + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.sc= r_el3), > + .writefn =3D scr_write }, > REGINFO_SENTINEL > }; >=20 > --=20 > 1.8.3.2 >=20