From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
liweiwei <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com
Subject: Re: [PATCH v6 4/6] target/riscv: Add support for PC-relative translation
Date: Tue, 4 Apr 2023 07:05:29 -0700 [thread overview]
Message-ID: <1a03c6de-9da3-c5ed-f59c-a90c5a07e97b@linaro.org> (raw)
In-Reply-To: <5c23fb0d-76d1-572c-a53a-d7e0d0e56643@linux.alibaba.com>
On 4/4/23 00:07, LIU Zhiwei wrote:
> Yes, I think so. I just suspect whether it is easy to read and verify the correctness. And
> the maintenance for the future.
>
>
> 1) Maybe we should split the PCREL to a split patch set, as it is a new feature. The point
> masking can still use this thread.
Yes.
> 2) For the new patch set for PCREL, process where we need to modify one by one. One clue
> for recognize where to modify is the ctx pc related fields, such as
> pc_next/pc_first/succ_insn_pc.
>
> One thing may worth to try is that don't change the code in insn_trans/trans_X. Just
> rename the origin API we need to modify to a new name with _abs suffix. And and a
> correspond set of API for PCREL with _pcrel suffix.
>
> For example, in DisasContext, we define
>
> void (*gen_set_gpri)(DisasContext *ctx, int reg_num, target_long imm);
>
> In disas_init_fn,
>
> if (tb_cflags(tb) & CF_PCREL) {
> gen_set_gpri = gen_set_gpri_pcrel;
> } else {
> gen_set_gpri = gen_set_gpri_abs;
> }
>
> Thus we can write the code in trans_insn without think about the PCREL.
No. Please have a look at how the other conversions have progressed. E.g.
https://lore.kernel.org/qemu-devel/20220930220312.135327-1-richard.henderson@linaro.org/
Step by step, each of the internal translation functions is converted from absolute to
relative values. By operating on relative values, all knowledge of "pc" is centralized,
and it simplifies the trans_* functions.
r~
next prev parent reply other threads:[~2023-04-04 14:05 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 2:06 [PATCH v6 0/6] target/riscv: Fix pointer mask related support Weiwei Li
2023-04-04 2:06 ` [PATCH v6 1/6] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-04-05 4:38 ` Alistair Francis
2023-04-04 2:06 ` [PATCH v6 2/6] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
2023-04-05 4:38 ` Alistair Francis
2023-04-04 2:06 ` [PATCH v6 3/6] target/riscv: Fix target address to update badaddr Weiwei Li
2023-04-04 3:06 ` LIU Zhiwei
2023-04-04 3:37 ` liweiwei
2023-04-05 4:41 ` Alistair Francis
2023-04-04 2:06 ` [PATCH v6 4/6] target/riscv: Add support for PC-relative translation Weiwei Li
2023-04-04 3:12 ` LIU Zhiwei
2023-04-04 3:25 ` LIU Zhiwei
2023-04-04 3:46 ` liweiwei
2023-04-04 7:07 ` LIU Zhiwei
2023-04-04 8:48 ` liweiwei
2023-04-04 9:23 ` LIU Zhiwei
2023-04-04 14:05 ` Richard Henderson [this message]
2023-04-04 13:56 ` Richard Henderson
2023-04-04 14:33 ` liweiwei
2023-04-04 14:57 ` Richard Henderson
2023-04-04 15:14 ` liweiwei
2023-04-04 15:27 ` Richard Henderson
2023-04-04 15:39 ` liweiwei
2023-04-04 2:06 ` [PATCH v6 5/6] target/riscv: Enable PC-relative translation in system mode Weiwei Li
2023-04-04 2:06 ` [PATCH v6 6/6] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
2023-04-04 2:52 ` LIU Zhiwei
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