* PCIE Memory Information
@ 2024-05-04 7:15 Muzammil Ashraf
2024-05-05 13:45 ` Aditya Gupta
0 siblings, 1 reply; 3+ messages in thread
From: Muzammil Ashraf @ 2024-05-04 7:15 UTC (permalink / raw)
To: qemu-devel
Hi All,
I am debugging a PCI subsystem. I saw callbacks registered here to
catch the pcie config read/write request at hw/pci/pci_host.c:201. How
can I make my subregion to overlap this area and How to receive those
pcie config read/write requests to my callbacks?
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: PCIE Memory Information
2024-05-04 7:15 PCIE Memory Information Muzammil Ashraf
@ 2024-05-05 13:45 ` Aditya Gupta
2024-05-05 17:19 ` Muzammil Ashraf
0 siblings, 1 reply; 3+ messages in thread
From: Aditya Gupta @ 2024-05-05 13:45 UTC (permalink / raw)
To: Muzammil Ashraf, qemu-devel
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Hi Ashraf,
On 04/05/24 12:45, Muzammil Ashraf wrote:
> Hi All,
>
> I am debugging a PCI subsystem. I saw callbacks registered here to
> catch the pcie config read/write request at hw/pci/pci_host.c:201. How
> can I make my subregion to overlap this area and How to receive those
> pcie config read/write requests to my callbacks?
>
Can go through this doc:
https://www.qemu.org/docs/master/devel/memory.html#overlapping-regions-and-priority
Normally the callbacks you mentioned will be registered on a
MemoryRegion. You can create your own MemoryRegion, and set your custom
.read, .write callbacks.
And setting the MemoryRegion's priority as a big positive number.
FWIW, had did something like this in past:
+static uint64_t adi_region_read(void *chip10, hwaddr addr, unsigned size) {
+ // your code
+}
+
+static void adi_region_write(void *chip10, hwaddr addr, uint64_t value,
unsigned size) {
+ // your code
+}
+
+static const MemoryRegionOps adi_region_ops = {
+ .read = adi_region_read,
+ .write = adi_region_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+ static hwaddr ADI_REGION_BASE = 0x0006010000000000ull + 0x100;
+
+ memory_region_init_io(&chip10->adi_region, OBJECT(chip10),
&adi_region_ops, chip10, "custom region: adityag", 0x100);
+ memory_region_add_subregion(get_system_memory(), ADI_REGION_BASE,
&chip10->adi_region);
Instead of 'get_system_memory', you will have to see what is the PCI
config region a subregion of.
Then, set the MemoryRegion's priority to some big number.
Then, you can verify if your overlapping was successful, with something
like this:
+ MemoryRegion *mr = address_space_translate(&address_space_memory,
ADI_REGION_BASE, &xlat, &l, false, MEMTXATTRS_UNSPECIFIED);
or
+ cpu_physical_memory_read(ADI_REGION_BASE, &val, 4);
1st should return your MemoryRegion, and second one should call your
.read callback.
Thanks,
Aditya Gupta
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: PCIE Memory Information
2024-05-05 13:45 ` Aditya Gupta
@ 2024-05-05 17:19 ` Muzammil Ashraf
0 siblings, 0 replies; 3+ messages in thread
From: Muzammil Ashraf @ 2024-05-05 17:19 UTC (permalink / raw)
To: Aditya Gupta; +Cc: qemu-devel
I have already studied this document and tested the overlap of MemoryRegions.
There is a structure named PCIHostState and in this struct there is a
field named config_reg. I want to understand where it gets changed.
On Sun, May 5, 2024 at 6:45 PM Aditya Gupta <adityag@linux.ibm.com> wrote:
>
> Hi Ashraf,
>
> On 04/05/24 12:45, Muzammil Ashraf wrote:
>
> Hi All,
>
> I am debugging a PCI subsystem. I saw callbacks registered here to
> catch the pcie config read/write request at hw/pci/pci_host.c:201. How
> can I make my subregion to overlap this area and How to receive those
> pcie config read/write requests to my callbacks?
>
>
> Can go through this doc: https://www.qemu.org/docs/master/devel/memory.html#overlapping-regions-and-priority
>
> Normally the callbacks you mentioned will be registered on a MemoryRegion. You can create your own MemoryRegion, and set your custom .read, .write callbacks.
>
> And setting the MemoryRegion's priority as a big positive number.
>
>
> FWIW, had did something like this in past:
>
>
> +static uint64_t adi_region_read(void *chip10, hwaddr addr, unsigned size) {
> + // your code
> +}
> +
> +static void adi_region_write(void *chip10, hwaddr addr, uint64_t value, unsigned size) {
> + // your code
> +}
> +
> +static const MemoryRegionOps adi_region_ops = {
> + .read = adi_region_read,
> + .write = adi_region_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .impl = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
>
> + static hwaddr ADI_REGION_BASE = 0x0006010000000000ull + 0x100;
> +
>
> + memory_region_init_io(&chip10->adi_region, OBJECT(chip10), &adi_region_ops, chip10, "custom region: adityag", 0x100);
> + memory_region_add_subregion(get_system_memory(), ADI_REGION_BASE, &chip10->adi_region);
>
> Instead of 'get_system_memory', you will have to see what is the PCI config region a subregion of.
>
>
> Then, set the MemoryRegion's priority to some big number.
>
> Then, you can verify if your overlapping was successful, with something like this:
>
>
> + MemoryRegion *mr = address_space_translate(&address_space_memory, ADI_REGION_BASE, &xlat, &l, false, MEMTXATTRS_UNSPECIFIED);
>
> or
>
> + cpu_physical_memory_read(ADI_REGION_BASE, &val, 4);
>
>
> 1st should return your MemoryRegion, and second one should call your .read callback.
>
>
> Thanks,
>
> Aditya Gupta
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-05-05 13:45 ` Aditya Gupta
2024-05-05 17:19 ` Muzammil Ashraf
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