From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: ardb@kernel.org, berrange@redhat.com, qemu-ppc@nongnu.org,
qemu-arm@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com
Subject: Re: [PATCH v2 02/38] util: Add cpuinfo-ppc.c
Date: Mon, 12 Jun 2023 10:27:14 -0300 [thread overview]
Message-ID: <1a7d9338-ec1f-0708-c4d0-930ff960d6bf@gmail.com> (raw)
In-Reply-To: <20230609022401.684157-3-richard.henderson@linaro.org>
On 6/8/23 23:23, Richard Henderson wrote:
> Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10
> is actually spelled PPC_FEATURE2_ARCH_3_1.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> host/include/ppc/host/cpuinfo.h | 29 ++++++++++++++++
> host/include/ppc64/host/cpuinfo.h | 1 +
> tcg/ppc/tcg-target.h | 16 ++++-----
> util/cpuinfo-ppc.c | 57 +++++++++++++++++++++++++++++++
> tcg/ppc/tcg-target.c.inc | 44 +-----------------------
> util/meson.build | 2 ++
> 6 files changed, 98 insertions(+), 51 deletions(-)
> create mode 100644 host/include/ppc/host/cpuinfo.h
> create mode 100644 host/include/ppc64/host/cpuinfo.h
> create mode 100644 util/cpuinfo-ppc.c
>
> diff --git a/host/include/ppc/host/cpuinfo.h b/host/include/ppc/host/cpuinfo.h
> new file mode 100644
> index 0000000000..7ec252ef52
> --- /dev/null
> +++ b/host/include/ppc/host/cpuinfo.h
> @@ -0,0 +1,29 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Host specific cpu indentification for ppc.
> + */
> +
> +#ifndef HOST_CPUINFO_H
> +#define HOST_CPUINFO_H
> +
> +/* Digested version of <cpuid.h> */
> +
> +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
> +#define CPUINFO_V2_06 (1u << 1)
> +#define CPUINFO_V2_07 (1u << 2)
> +#define CPUINFO_V3_00 (1u << 3)
> +#define CPUINFO_V3_10 (1u << 4)
> +#define CPUINFO_ISEL (1u << 5)
> +#define CPUINFO_ALTIVEC (1u << 6)
> +#define CPUINFO_VSX (1u << 7)
> +
> +/* Initialized with a constructor. */
> +extern unsigned cpuinfo;
> +
> +/*
> + * We cannot rely on constructor ordering, so other constructors must
> + * use the function interface rather than the variable above.
> + */
> +unsigned cpuinfo_init(void);
> +
> +#endif /* HOST_CPUINFO_H */
> diff --git a/host/include/ppc64/host/cpuinfo.h b/host/include/ppc64/host/cpuinfo.h
> new file mode 100644
> index 0000000000..2f036a0627
> --- /dev/null
> +++ b/host/include/ppc64/host/cpuinfo.h
> @@ -0,0 +1 @@
> +#include "host/include/ppc/host/cpuinfo.h"
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index c7552b6391..b632a5a647 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -25,6 +25,8 @@
> #ifndef PPC_TCG_TARGET_H
> #define PPC_TCG_TARGET_H
>
> +#include "host/cpuinfo.h"
> +
> #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
>
> #define TCG_TARGET_NB_REGS 64
> @@ -61,14 +63,12 @@ typedef enum {
> tcg_isa_3_10,
> } TCGPowerISA;
>
> -extern TCGPowerISA have_isa;
> -extern bool have_altivec;
> -extern bool have_vsx;
> -
> -#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
> -#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
> -#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
> -#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
> +#define have_isa_2_06 (cpuinfo & CPUINFO_V2_06)
> +#define have_isa_2_07 (cpuinfo & CPUINFO_V2_07)
> +#define have_isa_3_00 (cpuinfo & CPUINFO_V3_00)
> +#define have_isa_3_10 (cpuinfo & CPUINFO_V3_10)
> +#define have_altivec (cpuinfo & CPUINFO_ALTIVEC)
> +#define have_vsx (cpuinfo & CPUINFO_VSX)
>
> /* optional instructions automatically implemented */
> #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
> diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
> new file mode 100644
> index 0000000000..ee761de33a
> --- /dev/null
> +++ b/util/cpuinfo-ppc.c
> @@ -0,0 +1,57 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Host specific cpu indentification for ppc.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "host/cpuinfo.h"
> +
> +#ifdef CONFIG_GETAUXVAL
> +# include <sys/auxv.h>
> +#else
> +# include <asm/cputable.h>
> +# include "elf.h"
> +#endif
> +
> +unsigned cpuinfo;
> +
> +/* Called both as constructor and (possibly) via other constructors. */
> +unsigned __attribute__((constructor)) cpuinfo_init(void)
> +{
> + unsigned info = cpuinfo;
> + unsigned long hwcap, hwcap2;
> +
> + if (info) {
> + return info;
> + }
> +
> + hwcap = qemu_getauxval(AT_HWCAP);
> + hwcap2 = qemu_getauxval(AT_HWCAP2);
> + info = CPUINFO_ALWAYS;
> +
> + if (hwcap & PPC_FEATURE_ARCH_2_06) {
> + info |= CPUINFO_V2_06;
> + }
> + if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
> + info |= CPUINFO_V2_07;
> + }
> + if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
> + info |= CPUINFO_V3_00;
> + }
> + if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
> + info |= CPUINFO_V3_10;
> + }
> + if (hwcap2 & PPC_FEATURE2_HAS_ISEL) {
> + info |= CPUINFO_ISEL;
> + }
> + if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
> + info |= CPUINFO_ALTIVEC;
> + /* We only care about the portion of VSX that overlaps Altivec. */
> + if (hwcap & PPC_FEATURE_HAS_VSX) {
> + info |= CPUINFO_VSX;
> + }
> + }
> +
> + cpuinfo = info;
> + return info;
> +}
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 5c8378f8f6..c866f2c997 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -101,10 +101,7 @@
> #define ALL_GENERAL_REGS 0xffffffffu
> #define ALL_VECTOR_REGS 0xffffffff00000000ull
>
> -TCGPowerISA have_isa;
> -static bool have_isel;
> -bool have_altivec;
> -bool have_vsx;
> +#define have_isel (cpuinfo & CPUINFO_ISEL)
>
> #ifndef CONFIG_SOFTMMU
> #define TCG_GUEST_BASE_REG 30
> @@ -3879,45 +3876,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
>
> static void tcg_target_init(TCGContext *s)
> {
> - unsigned long hwcap = qemu_getauxval(AT_HWCAP);
> - unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
> -
> - have_isa = tcg_isa_base;
> - if (hwcap & PPC_FEATURE_ARCH_2_06) {
> - have_isa = tcg_isa_2_06;
> - }
> -#ifdef PPC_FEATURE2_ARCH_2_07
> - if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
> - have_isa = tcg_isa_2_07;
> - }
> -#endif
> -#ifdef PPC_FEATURE2_ARCH_3_00
> - if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
> - have_isa = tcg_isa_3_00;
> - }
> -#endif
> -#ifdef PPC_FEATURE2_ARCH_3_10
> - if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
> - have_isa = tcg_isa_3_10;
> - }
> -#endif
> -
> -#ifdef PPC_FEATURE2_HAS_ISEL
> - /* Prefer explicit instruction from the kernel. */
> - have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0;
> -#else
> - /* Fall back to knowing Power7 (2.06) has ISEL. */
> - have_isel = have_isa_2_06;
> -#endif
> -
> - if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
> - have_altivec = true;
> - /* We only care about the portion of VSX that overlaps Altivec. */
> - if (hwcap & PPC_FEATURE_HAS_VSX) {
> - have_vsx = true;
> - }
> - }
> -
> tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
> tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
> if (have_altivec) {
> diff --git a/util/meson.build b/util/meson.build
> index 3a93071d27..a375160286 100644
> --- a/util/meson.build
> +++ b/util/meson.build
> @@ -113,4 +113,6 @@ if cpu == 'aarch64'
> util_ss.add(files('cpuinfo-aarch64.c'))
> elif cpu in ['x86', 'x86_64']
> util_ss.add(files('cpuinfo-i386.c'))
> +elif cpu in ['ppc', 'ppc64']
> + util_ss.add(files('cpuinfo-ppc.c'))
> endif
next prev parent reply other threads:[~2023-06-12 13:28 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-09 2:23 [PATCH v2 00/38] crypto: Provide aes-round.h and host accel Richard Henderson
2023-06-09 2:23 ` [PATCH v2 01/38] tcg/ppc: Define _CALL_AIX for clang on ppc64(be) Richard Henderson
2023-06-12 13:25 ` Daniel Henrique Barboza
2023-06-09 2:23 ` [PATCH v2 02/38] util: Add cpuinfo-ppc.c Richard Henderson
2023-06-12 13:27 ` Daniel Henrique Barboza [this message]
2023-06-19 10:37 ` Philippe Mathieu-Daudé
2023-06-19 14:44 ` Richard Henderson
2023-06-09 2:23 ` [PATCH v2 03/38] tests/multiarch: Add test-aes Richard Henderson
2023-06-12 14:46 ` Alex Bennée
2023-06-14 3:40 ` Richard Henderson
2023-06-09 2:23 ` [PATCH v2 04/38] target/arm: Move aesmc and aesimc tables to crypto/aes.c Richard Henderson
2023-06-19 16:49 ` Daniel P. Berrangé
2023-06-09 2:23 ` [PATCH v2 05/38] crypto/aes: Add constants for ShiftRows, InvShiftRows Richard Henderson
2023-06-19 15:41 ` Daniel P. Berrangé
2023-06-29 10:21 ` Ard Biesheuvel
2023-06-29 11:58 ` Richard Henderson
2023-06-09 2:23 ` [PATCH v2 06/38] crypto: Add aesenc_SB_SR_AK Richard Henderson
2023-06-19 16:56 ` Daniel P. Berrangé
2023-06-19 17:05 ` Richard Henderson
2023-06-09 2:23 ` [PATCH v2 07/38] target/i386: Use aesenc_SB_SR_AK Richard Henderson
2023-06-19 10:43 ` Philippe Mathieu-Daudé
2023-06-19 10:45 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 08/38] target/arm: Demultiplex AESE and AESMC Richard Henderson
2023-06-09 2:23 ` [PATCH v2 09/38] target/arm: Use aesenc_SB_SR_AK Richard Henderson
2023-06-09 2:23 ` [PATCH v2 10/38] target/ppc: " Richard Henderson
2023-06-12 13:26 ` Daniel Henrique Barboza
2023-06-19 10:47 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 11/38] target/riscv: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 12/38] crypto: Add aesdec_ISB_ISR_AK Richard Henderson
2023-06-09 2:23 ` [PATCH v2 13/38] target/i386: Use aesdec_ISB_ISR_AK Richard Henderson
2023-06-19 10:51 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 14/38] target/arm: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 15/38] target/ppc: " Richard Henderson
2023-06-12 13:27 ` Daniel Henrique Barboza
2023-06-19 10:51 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 16/38] target/riscv: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 17/38] crypto: Add aesenc_MC Richard Henderson
2023-06-09 2:23 ` [PATCH v2 18/38] target/arm: Use aesenc_MC Richard Henderson
2023-06-09 2:23 ` [PATCH v2 19/38] crypto: Add aesdec_IMC Richard Henderson
2023-06-09 2:23 ` [PATCH v2 20/38] target/i386: Use aesdec_IMC Richard Henderson
2023-06-09 2:23 ` [PATCH v2 21/38] target/arm: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 22/38] target/riscv: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 23/38] crypto: Add aesenc_SB_SR_MC_AK Richard Henderson
2023-06-09 2:23 ` [PATCH v2 24/38] target/i386: Use aesenc_SB_SR_MC_AK Richard Henderson
2023-06-09 2:23 ` [PATCH v2 25/38] target/ppc: " Richard Henderson
2023-06-12 13:28 ` Daniel Henrique Barboza
2023-06-09 2:23 ` [PATCH v2 26/38] target/riscv: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 27/38] crypto: Add aesdec_ISB_ISR_IMC_AK Richard Henderson
2023-06-09 2:23 ` [PATCH v2 28/38] target/i386: Use aesdec_ISB_ISR_IMC_AK Richard Henderson
2023-06-09 2:23 ` [PATCH v2 29/38] target/riscv: " Richard Henderson
2023-06-09 2:23 ` [PATCH v2 30/38] crypto: Add aesdec_ISB_ISR_AK_IMC Richard Henderson
2023-06-19 13:59 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 31/38] target/ppc: Use aesdec_ISB_ISR_AK_IMC Richard Henderson
2023-06-12 13:28 ` Daniel Henrique Barboza
2023-06-19 13:46 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 32/38] crypto: Remove AES_shifts, AES_ishifts Richard Henderson
2023-06-19 13:45 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 33/38] crypto: Implement aesdec_IMC with AES_imc_rot Richard Henderson
2023-06-20 5:09 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 34/38] crypto: Remove AES_imc Richard Henderson
2023-06-19 13:19 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 35/38] crypto: Unexport AES_*_rot, AES_TeN, AES_TdN Richard Henderson
2023-06-19 13:18 ` Philippe Mathieu-Daudé
2023-06-09 2:23 ` [PATCH v2 36/38] host/include/i386: Implement aes-round.h Richard Henderson
2023-06-09 2:24 ` [PATCH v2 37/38] host/include/aarch64: " Richard Henderson
2023-06-09 2:24 ` [PATCH v2 38/38] host/include/ppc: " Richard Henderson
2023-06-12 13:30 ` Daniel Henrique Barboza
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