From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Zhenzhong Duan" <zhenzhong.duan@intel.com>,
"Yi Sun" <yi.y.sun@linux.intel.com>,
"Jason Wang" <jasowang@redhat.com>,
"Clément Mathieu--Drif" <clement.mathieu--drif@eviden.com>,
"Yi Liu" <yi.l.liu@intel.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>
Subject: [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap
Date: Wed, 15 Jan 2025 13:09:27 -0500 [thread overview]
Message-ID: <1ab93575bdcb2972c99a174a957b598f7457a899.1736964488.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1736964487.git.mst@redhat.com>
From: Zhenzhong Duan <zhenzhong.duan@intel.com>
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
There is already a similar implementation in iotlb invalidation.
So update vtd_iotlb_page_invalidate_notify() to make it work
also for piotlb invalidation.
For device that does not implement ATS capability or disable
it but still caches the translation result, it is better to
implement ATS cap or enable it if there is need to cache the
translation result.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-15-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/intel_iommu.c | 43 ++++++++++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 5634a37a74..7d4b99523d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2450,8 +2450,13 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
}
}
+/*
+ * There is no pasid field in iotlb invalidation descriptor, so PCI_NO_PASID
+ * is passed as parameter. Piotlb invalidation supports pasid, pasid in its
+ * descriptor is passed which should not be PCI_NO_PASID.
+ */
static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
- uint16_t domain_id, hwaddr addr,
+ uint16_t domain_id, hwaddr addr,
uint8_t am, uint32_t pasid)
{
VTDAddressSpace *vtd_as;
@@ -2460,19 +2465,37 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
hwaddr size = (1 << am) * VTD_PAGE_SIZE;
QLIST_FOREACH(vtd_as, &(s->vtd_as_with_notifiers), next) {
- if (pasid != PCI_NO_PASID && pasid != vtd_as->pasid) {
- continue;
- }
ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
vtd_as->devfn, &ce);
if (!ret && domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
+ uint32_t rid2pasid = PCI_NO_PASID;
+
+ if (s->root_scalable) {
+ rid2pasid = VTD_CE_GET_RID2PASID(&ce);
+ }
+
+ /*
+ * In legacy mode, vtd_as->pasid == pasid is always true.
+ * In scalable mode, for vtd address space backing a PCI
+ * device without pasid, needs to compare pasid with
+ * rid2pasid of this device.
+ */
+ if (!(vtd_as->pasid == pasid ||
+ (vtd_as->pasid == PCI_NO_PASID && pasid == rid2pasid))) {
+ continue;
+ }
+
if (vtd_as_has_map_notifier(vtd_as)) {
/*
- * As long as we have MAP notifications registered in
- * any of our IOMMU notifiers, we need to sync the
- * shadow page table.
+ * When stage-1 translation is off, as long as we have MAP
+ * notifications registered in any of our IOMMU notifiers,
+ * we need to sync the shadow page table. Otherwise VFIO
+ * device attaches to nested page table instead of shadow
+ * page table, so no need to sync.
*/
- vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size);
+ if (!s->flts || !s->root_scalable) {
+ vtd_sync_shadow_page_table_range(vtd_as, &ce, addr, size);
+ }
} else {
/*
* For UNMAP-only notifiers, we don't need to walk the
@@ -2960,7 +2983,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
continue;
}
- if (!s->flts) {
+ if (!s->flts || !vtd_as_has_map_notifier(vtd_as)) {
vtd_address_space_sync(vtd_as);
}
}
@@ -2981,6 +3004,8 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
g_hash_table_foreach_remove(s->iotlb,
vtd_hash_remove_by_page_piotlb, &info);
vtd_iommu_unlock(s);
+
+ vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid);
}
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
--
MST
next prev parent reply other threads:[~2025-01-15 18:19 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 02/48] pci: ensure valid link status bits for downstream ports Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 03/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 05/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 07/48] intel_iommu: Make pasid entry type check accurate Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 10/48] intel_iommu: Rename slpte to pte Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 11/48] intel_iommu: Implement stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 12/48] intel_iommu: Check if the input address is canonical Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 16/48] intel_iommu: Process PASID-based " Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation Michael S. Tsirkin
2025-01-15 18:09 ` Michael S. Tsirkin [this message]
2025-01-15 18:09 ` [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 22/48] tests/acpi: q35: Update host address width in DMAR Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 25/48] tests/qtest: Add intel-iommu test Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 30/48] acpi/ghes: better handle source_id and notification Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 33/48] acpi/ghes: Change the type for source_id Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 34/48] acpi/ghes: don't check if physical_address is not zero Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 35/48] acpi/ghes: make the GHES record generation more generic Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 36/48] acpi/ghes: better name GHES memory error function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 40/48] acpi/ghes: move offset calculus to a separate function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 43/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 45/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr` Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 47/48] vhost: Add stubs for the migration state transfer interface Michael S. Tsirkin
2025-01-15 18:11 ` [PULL 48/48] virtio-net: vhost-user: Implement internal migration Michael S. Tsirkin
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
2025-01-15 22:42 ` Michael S. Tsirkin
2025-01-15 23:05 ` David Woodhouse
2025-01-16 7:05 ` Michael S. Tsirkin
2025-01-16 14:06 ` David Woodhouse
2025-01-16 7:06 ` Michael S. Tsirkin
2025-01-16 22:10 ` Stefan Hajnoczi
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