From: Richard Henderson <rth@twiddle.net>
To: Artyom Tarasenko <atar4qemu@gmail.com>
Cc: qemu-devel <qemu-devel@nongnu.org>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: Re: [Qemu-devel] [PATCH v3 00/15] target-sparc improvements
Date: Mon, 31 Oct 2016 10:06:10 -0600 [thread overview]
Message-ID: <1af05887-d03c-d55e-5ff7-c7294e19941d@twiddle.net> (raw)
In-Reply-To: <CACXAS8APkbcL=mzfDPeJM6jaAjPbdc55FZ9_Rg=RnBttTihJ0A@mail.gmail.com>
On 10/31/2016 09:40 AM, Artyom Tarasenko wrote:
>> * The "Remove asi helper code handled inline" patch retains the code within
>> ldda to handle asis that must be handled out of line. This fixes the
>> FreeBSD 10.3 boot problem. While the UA2007 spec (and thus sun4v?) doesn't
>> allow for such, it would seem that US2 hardware does.
>
> What ASI was failing? It may still be a part of sun4v CPUs if it's
> described in UST1/UST2 supplements.
0x00000000c08e5680: clr %g4
0x00000000c08e5684: mov 1, %g1
0x00000000c08e5688: sllx %g1, 0x24, %o5
0x00000000c08e568c: mov -1, %g1
0x00000000c08e5690: sllx %g1, 0x23, %g1
0x00000000c08e5694: xor %g1, -128, %o4
0x00000000c08e5698: ldda [ %g4 ] #ASI_IC_TAG, %g0 ****
0x00000000c08e569c: mov %g1, %g2
0x00000000c08e56a0: and %g1, %o5, %g1
0x00000000c08e56a4: brz,a %g1, 0xc08e56dc
So indeed it would appear that FreeBSD does in fact want the half of the result
that would get stored into %g1. As far as I can see they could have achieved
the same result with
ldxa [%g4] #ASI_IC_TAG, %g1
srl %g1, 0, %g1
to stay within the nominal spec.
r~
next prev parent reply other threads:[~2016-10-31 16:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-27 17:07 [Qemu-devel] [PATCH v3 00/15] target-sparc improvements Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 01/15] target-sparc: Use overalignment flags for twinx and block asis Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 02/15] target-sparc: Introduce cpu_raise_exception_ra Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 03/15] target-sparc: Add MMU_PHYS_IDX Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 05/15] target-sparc: Handle more twinx asis Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 06/15] target-sparc: Implement swap_asi inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 07/15] target-sparc: Implement ldstub_asi inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 08/15] target-sparc: Implement cas_asi/casx_asi inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 09/15] target-sparc: Implement BCOPY/BFILL inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 10/15] target-sparc: Remove asi helper code handled inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 11/15] target-sparc: Implement ldqf and stqf inline Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 12/15] target-sparc: Allow 4-byte alignment on fp mem ops Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 13/15] target-sparc: Remove MMU_MODE*_SUFFIX Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 14/15] target-sparc: Use tcg_gen_atomic_xchg_tl Richard Henderson
2016-10-27 17:07 ` [Qemu-devel] [PATCH v3 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl Richard Henderson
2016-10-28 14:22 ` [Qemu-devel] [PATCH v3 00/15] target-sparc improvements Mark Cave-Ayland
2016-10-31 15:40 ` Artyom Tarasenko
2016-10-31 16:06 ` Richard Henderson [this message]
2016-10-31 16:21 ` Artyom Tarasenko
2016-10-31 16:32 ` Richard Henderson
2016-10-31 17:31 ` Artyom Tarasenko
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